JP2001343432A - Boundary scanning circuit and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rapidly and surely provide a boundary scanning circuit, capable of inspecting the mounting or connection failures of a plurality of the integrated circuit devices on a substrate circuit, without having to form complicated circuit configuration. SOLUTION: Test data input(TDI signal), supplied from an external inspection apparatus (not shown), is respectively inputted to the TDI terminals of integrated circuit devices 1, 2, 3 in parallel. A selector 5 selects the TDO(test data output) signal of the integrated circuit device to be inspected from among the test data (TDO signals), outputted from the TDO terminals of the integrated circuit devices 1, 2, 3 corresponding to the selection signal Ss supplied from the external inspection apparatus, to send the same to the external inspection apparatus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boundary scan circuit and a method therefor, and more particularly to a boundary scan circuit and a method applied to inspection of a mounting failure or a connection failure of a substrate circuit on which a plurality of integrated circuit devices are mounted. .

[0002]

2. Description of the Related Art Since the degree of integration of integrated circuit devices has been improved and their dimensions have been reduced, when checking the operation of a substrate circuit on which a plurality of integrated circuit devices are mounted or inspecting the connection state, etc. It has become difficult to connect probes directly to pins of integrated circuit devices. Particularly, a QFP package (Quad Flat Pac) with a narrow pin interval
Kage) and BGA package (Ball Grid)
In a board circuit on which a plurality of integrated circuit devices such as Array) are mounted, the pins cannot be brought into contact with the probe.

As a method of checking the operation of the board circuit and checking the connection state, a boundary scan (Boundary scan) is used.
(Ary Scan) is applied.

FIG. 3 is a block diagram showing an example of a conventional boundary scan circuit, in which a plurality of integrated circuit devices are mounted on a substrate circuit. Here, to simplify the drawing, three integrated circuit devices 1, 2, 2,
3 is shown.

Each of the integrated circuit devices 1, 2, and 3 has an internal logic, an input terminal (PI terminal) for receiving data input in parallel, an output terminal (PO terminal) for outputting data in parallel, and an external terminal. A test data input terminal (TDI (Test Data Input) terminal) of a boundary scan which is serially input from an inspection device (not shown) and an output terminal (TDO (Test) of test data)
(Data Output) terminal), a boundary scan cell (BSC) for holding and transferring test data, and a TMS signal (TMS: Test Mode Select) and a TCK signal (TCK: TCK) supplied from an external inspection device (not shown). A test access port (TAP) for transmitting test data to the route of the BSC or bypassing or controlling the test data via a bypass register (BYP) is provided in accordance with the Test Clock (Test Clock K).

[0006] The BSC is provided corresponding to the PI terminal and the PO terminal, respectively. In FIG. 3, five terminals are provided corresponding to the PI terminal side and the PO terminal side. During the test, the test data serially input from the TDI terminal is serially transferred to the TDO terminal and output, or the data input in parallel to the PI terminal is temporarily stored and then serially transmitted to the TDO terminal. And test data input serially from the TDI terminal is output to the BS on the PO terminal side.
C and output in parallel from the PO terminal.

In a conventional example, as shown in FIG. 3, a TDI terminal and a TDI terminal between a plurality of integrated circuit devices on a substrate circuit are provided.
The DO terminals are connected in series so that one scan path is formed.

That is, the test data input terminal (not shown) of the substrate circuit is connected to the TDI terminal of the integrated circuit device 1, the TDO terminal of the integrated circuit device 1 is connected to the TDI terminal of the integrated circuit device 2, The TDO terminal of the integrated circuit device 2 is connected to the TDI terminal of the integrated circuit device 3, and the TDO terminal of the integrated circuit device 3 is connected to a test data output terminal (not shown) of the substrate circuit.

When a connection failure of an integrated circuit device on a substrate circuit is inspected by a boundary scan, input test data (TDI signal generated by an external inspection device (not shown)) is applied to a TDI terminal of the integrated circuit device 1. )
Enter

For example, if there is a poor connection P between the second PO terminal of the integrated circuit device 1 and the fourth PI terminal of the integrated circuit device 2, 5
The bit data “11111” is serially input to the TDI terminal of the integrated circuit device 1. Then, after the data is transferred to the BSC on the PO terminal side via the BSC of the integrated circuit device 1, the data “11” is transferred to the BSC on the PI terminal side of the integrated circuit device 2 via the PO terminal of the integrated circuit device 1.
111 "in parallel.

At this time, there is a connection failure between the second PO terminal of the integrated circuit device 1 and the fourth PI terminal of the integrated circuit device 2, and the connection failure of the integrated circuit device 2 corresponding to this connection failure location. The data "1" is not transmitted to the BSC of the fourth PI terminal, and the original data "0" remains. Therefore, the data serially transferred from the BSC on the PI terminal side of the integrated circuit device 2 to the TDO terminal is “10111”. By extracting this data via the bypass register of the integrated circuit device 3,
The location of the connection failure can be specified.

[0012]

As described above, in the conventional example, when a plurality of integrated circuit devices on a substrate circuit are inspected for mounting failure or connection failure by a boundary scan,
A scan path is formed so that input test data (TDI signal) passes in series through all of the integrated circuit devices. However, when the scan path is opened (disconnected) between the TDO terminal of some integrated circuit devices and the TDI terminal of the next integrated circuit device due to a mounting failure or a connection failure of the integrated circuit device, for example, in FIG. TDO terminal of integrated circuit device 2 and TDI of integrated circuit device 3
When the Q point between the terminal and the terminal is opened (disconnected), the output test data cannot be obtained, so that the inspection cannot be performed.

[0013] In addition, there is a problem in that, when an individual test is performed for each integrated circuit device, the test becomes complicated.

An object of the present invention is to provide a method for reliably and easily forming a plurality of integrated circuit devices on a substrate circuit even if a scan path is opened (disconnected) in some integrated circuit devices without a complicated circuit configuration. An object of the present invention is to provide a boundary scan circuit capable of inspecting a mounting failure, a connection failure, and the like, and a method thereof.

[0015]

SUMMARY OF THE INVENTION A boundary scan circuit according to the present invention is provided for detecting a mounting failure or a connection failure of a substrate circuit on which a plurality of integrated circuit devices having a boundary scan cell (BSC) corresponding to a pin terminal are mounted. In a boundary scan circuit to be inspected, input test data generated by an external inspection device and serially input to the substrate circuit is supplied in parallel to test data input terminals of the plurality of integrated circuit devices, respectively, and the plurality of integrated circuits are A selector is provided for selecting one of the output test data output from the test data output terminals of the device and sending it to the external inspection device. The selector receives the selection signal supplied from the external inspection device and selects the output test data.

Further, when the external test device transmits the input test data including the selection information bit of the selector, the selection information bit is extracted from the input test data to generate the selection signal. Signal generating means; Specifically, a specific one of the plurality of integrated circuit devices that receives the input test data and extracts the selection information bit as a parallel bit, and receives the parallel bit and generates the selection signal. And a decoder circuit for generating.

A boundary scan method according to the present invention is a boundary scan method for inspecting a mounting failure or a connection failure of a substrate circuit on which a plurality of integrated circuit devices having a boundary scan cell (BSC) corresponding to a pin terminal are mounted. Input test data generated by an external inspection device and serially input to the substrate circuit is supplied in parallel to test data input terminals of the plurality of integrated circuit devices, and test data output terminals of the plurality of integrated circuit devices are supplied. Select one of the output test data respectively output from.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. For simplicity of the drawing, a case is shown in which three integrated circuit devices 1, 2, 3 are mounted on a substrate circuit.

Each of the integrated circuit devices 1, 2, 3 has a structure shown in FIG.
As in the conventional example shown in FIG. 1, an internal logic, an input terminal (PI terminal) for receiving data input in parallel, an output terminal (PO terminal) for outputting data in parallel, and an external inspection device (not shown) ) Serially input from boundary test data input terminal (TDI terminal)
, A test data output terminal (TDO terminal), and a boundary scan cell (BS) for holding and transferring the test data.
C) and T supplied from an external inspection device (not shown).
MS signal (TMS: Test Mode Select)
t) and TCK signal (TCK: Test Clock)
According to K), a test access port (TAP) for sending test data to the BSC route or bypassing and controlling the test data via a bypass register (BYP) is provided.

The BSC is provided corresponding to each of the PI terminal and the PO terminal.
Test data serially input from DI terminal is TD
After serially transferring and outputting the data to the O terminal, or temporarily storing the data input in parallel to the PI terminal,
Serially transferred to DO terminal and output, or
Test data input serially from the TDI terminal
The data is transferred to the BSC on the O terminal side and output in parallel from the PO terminal.

The difference from the conventional example shown in FIG.
Input test data (TDI signal) supplied from an external inspection device (not shown) is transmitted to each of the integrated circuit devices 1, 2, 2, and 3.
3 is input in parallel to each TDI terminal.

The test data (TDO signal) output from the TDO terminal of each integrated circuit device is:
The point is that one of them is selected by the selector 5 and sent to an external inspection device.

Here, the selector 5 operates in response to a selection signal Ss supplied from an external inspection device, and selects the TD of the integrated circuit device to be inspected from among the plurality of integrated circuit devices.
Select one O signal.

Next, the operation will be described.

When performing the boundary scan, a TDI signal supplied from an external inspection device is input in parallel to the TDI terminals of the integrated circuit devices 1, 2, and 3, respectively.
In addition, the selector 5 responds to the selection signal Ss output from the external inspection device to set the T.sub.T of the integrated circuit device to be inspected.
The TDO signal output from the DO terminal is selected and sent to an external inspection device.

Now, for example, the PO of the integrated circuit device 1
Terminal of the second terminal and fourth terminal of the PI terminal of the integrated circuit device 2.
If there is a defective connection point P between the second and the third, the defective connection point can be specified as follows.

That is, first, 5-bit serial data “11111” is input as input test data (TDI signal) from an external inspection apparatus to each integrated circuit device 1,
Input to the TDI terminals 2 and 3, respectively. In addition, a selector 5 sends a TDO selection signal from an external inspection device,
The output data (TDO) of the TDO terminal of the integrated circuit device 2
Signal) is selected by the selector 5.

Then, in each integrated circuit device, T
Test data “111” serially input to the DI terminal
11 "is transferred to the BSC on the PO terminal side via the BSC, and then output in parallel to the PI terminals of other integrated circuit devices connected to these PO terminals.

At this time, in the integrated circuit device 1, the test data “11111” serially input to the TDI terminal is transmitted to the PO terminal side BSC via the BSC.
After that, the data “11111” is output in parallel to the PI terminal of the integrated circuit device 2 connected to these PO terminals.

At this time, since there is a poor connection point P between the second PO terminal of the integrated circuit device 1 and the fourth PI terminal of the integrated circuit device 2, the integrated circuit corresponding to the poor connection point The data “1” is not transmitted to the BSC of the fourth PI terminal of the device 2, and the original data “0” remains. Therefore, the data serially transferred from the BSC on the PI terminal side of the integrated circuit device 2 to the TDO terminal is “10111”.

The integrated circuit device 2 converts the data “10111” input in parallel to the BSC via the PI terminal into T
Transfer and output to DO terminal. The selector 5 selects the data “10111” serially output from the TDO terminal of the integrated circuit device 2 and sends it to an external inspection device. The external inspection device compares the data “11111” sent to the substrate circuit with the data “10111” serially output from the TDO terminal of the integrated circuit device 2 to analyze a connection failure portion.

By switching the TDO terminals of a plurality of integrated circuit devices mounted on the substrate circuit by the selector 5 in order, the inspection can be performed for all the integrated circuit devices.

As described above, the test data is input in parallel to the TDI terminals of the plurality of integrated circuit devices on the substrate circuit, and the data from the TDO terminal of the integrated circuit device to be inspected among the plurality of integrated circuit devices is transferred. By selecting with the selector, a scan path in which only one integrated circuit device is always selected can be made. Therefore, even if a scan path between some integrated circuit devices is open (disconnected), other integrated circuit devices are opened. Inspection of circuit devices becomes possible.

For example, in FIG. 1, even if the Q point on the TDO terminal side of the integrated circuit device 2 is open (disconnected), the integrated circuit devices 1 and 3 can be inspected.

Further, even if a plurality of integrated circuit devices have a mounting defect, a connection defect, or the like, the inspection can be performed reliably and easily without a complicated circuit configuration.

Although the selector 5 is an electrically operated switch in the above description, the circuit configuration can be further simplified by using a mechanical switch or a jumper pin.

FIG. 2 is a block diagram showing another embodiment.

The same components as those shown in FIG. 1 are denoted by the same reference numerals. The difference from the embodiment shown in FIG. 1 is that the selection signal to be supplied to the selector 5 is generated in the substrate circuit.

For this purpose, a dedicated integrated circuit device 4 for extracting a bit including selection information included in input test data from an external tester at the time of a test, and a selection information extracted by the integrated circuit device 4 are included. And a decoder circuit 6 for generating a selection signal Ss to be supplied to the selector 5 based on a plurality of bits.

The input test data from the external inspection apparatus is input to the TDI terminal of the integrated circuit device 4, and is connected to the TDO terminal of the integrated circuit device 4 and the other integrated circuit devices 1,
Each of the TDI terminals 2 and 3 is connected in parallel.

Here, the integrated circuit device 4 has the same configuration as the other integrated circuit devices 1, 2, 3 and performs normal data processing except during the test.

A plurality of predetermined terminals among the PO terminals of the integrated circuit device 4 are connected to the decoder circuit 6, and the decoder circuit 6 includes a plurality of terminals held by the BSC corresponding to the plurality of predetermined terminals. Receives bit data in parallel. Then, the selection signal Ss supplied to the selector 5
Generate Note that the number of bits that the decoder circuit 6 receives in parallel from the BSC of the integrated circuit device 4 is determined according to the number of signals selected by the selector 5. In FIG. 2, since the decoder circuit 6 receives 3-bit data in parallel, it is possible to generate a selection signal having a maximum of eight selectable signals.

Next, the operation will be described.

First, a selection signal Ss for selecting an integrated circuit device to be inspected is supplied to the selector 5. For this purpose, first, input test data (TDI signal) including selection information is generated by an external inspection device, and the integrated circuit device 4 is generated.
Is serially input to the TDI terminal. For example, when selecting the TDO terminal of the integrated circuit device 3, 5-bit data “00011” including the selection information “3” is serially input to the TDI terminal of the integrated circuit device 4.

The integrated circuit device 4 transfers the data serially input to the TDI terminal to the BSC on the PO terminal side,
Data including this selection information is sent to the decoder circuit 6 in parallel from the first to third PO terminals. The decoder circuit 6 outputs the parallel data “00” from the integrated circuit device 4.
11 ”, the selection signal Ss for selecting the TDO terminal of the integrated circuit device 3 is supplied to the selector 5.

Thereafter, when executing the boundary scan, the integrated circuit device 4 executes the boundary scan in the same manner as the embodiment shown in FIG. 1 by bypassing the data input to the TDI terminal to the TDO terminal as it is.

By doing so, the selection signal Ss
Can be generated in the substrate circuit and the boundary scan can be executed, so that the selection signal S
A transmission line for receiving s is unnecessary.

[0049]

As described above, according to the present invention, test data is input in parallel to the TDI terminals of a plurality of integrated circuit devices on a substrate circuit, and the test object integrated among the plurality of integrated circuit devices is tested. By selecting data from the TDO terminal of the circuit device by the selector, a scan path in which only one integrated circuit device is selected can always be created. Can be prevented from being untestable due to the opening (disconnection) of.

Further, by generating the selection signal to be supplied to the selector in the substrate circuit, a transmission line for receiving the selection signal from an external inspection device becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a conventional boundary scan circuit.

[Explanation of symbols]

 1,2,3,4 integrated circuit device 5 selector 6 decoder circuit

Claims (8)

[Claims] 1. A boundary scan circuit for inspecting a mounting failure or a connection failure of a substrate circuit on which a plurality of integrated circuit devices having a boundary scan cell (BSC) corresponding to a pin terminal is mounted by an external inspection device. A boundary scan circuit, wherein input test data generated and serially input to the substrate circuit is supplied in parallel to test data input terminals of the plurality of integrated circuit devices, respectively. 2. The semiconductor device according to claim 1, further comprising a selector for selecting one of output test data output from test data output terminals of the plurality of integrated circuit devices and transmitting the selected output test data to the external inspection apparatus. 2. The boundary scan circuit according to 1. 3. The selector according to claim 2, wherein the selector receives the selection signal and selects the output test data.
The described boundary scan circuit. 4. The boundary scan circuit according to claim 3, wherein said selector receives the selection signal supplied from said external inspection device and selects said output test data. 5. A selection method for extracting the selection information bits from the input test data and generating the selection signal when the external inspection device transmits the input test data including the selection information bits of the selector. 4. The boundary scan circuit according to claim 3, further comprising a signal generation unit. 6. The integrated signal device according to claim 1, wherein the selection signal generating unit receives the input test data and extracts the selection information bit as a parallel bit. 6. A boundary scan circuit according to claim 5, further comprising: a decoder circuit for receiving said selection signal and generating said selection signal. 7. The boundary scan circuit according to claim 2, wherein the selector is a switch that operates mechanically. 8. A boundary scan method for inspecting a mounting failure or a connection failure of a substrate circuit on which a plurality of integrated circuit devices having a boundary scan cell (BSC) corresponding to pin terminals is mounted, using an external inspection device. Input test data generated and input serially to the substrate circuit is supplied in parallel to test data input terminals of the plurality of integrated circuit devices, and outputs respectively output from test data output terminals of the plurality of integrated circuit devices A boundary scan method, wherein one of the test data is selected.