JPH0670777B2 - Pseudo-fault occurrence method for information processing equipment - Google Patents

Description

The present invention relates to a pseudo failure generation method, and more particularly to a pseudo failure generation method for an information processing apparatus having a self-diagnosis / recovery function.

[Conventional technology]

When shipping information processing equipment products, it is necessary to inspect and confirm the normality of all the functions in advance.
It is difficult to test the malfunction detection mechanism, especially the re-execution function. That is, since the device is naturally designed so as not to malfunction in a normal state, the normality of the detection mechanism cannot be normally verified. Also,
Since the re-execution function assumes intermittent malfunction, it becomes more difficult to verify.

Conventionally, there are the following failure generation methods for verifying the malfunction detection mechanism and the re-execution function of the device.

(1) Reverse parity method A method in which a parity bit is forcibly inverted to cause a failure.

(2) Master check method A method in which a master check output, which is an assembly of check latches, is set to 1 to cause a failure.

(3) Error-injection method Specify the address compare address and the latch you want to generate a failure from the panel or service processor, and force the latch specified above when the micro instruction address or the instruction address and the address compare address match. Method to turn on the light.

(4) One-shot scan-in method A scan means provided for setting initial information and logging out of the processing device, in particular, using the scan-in function, a 1-bit register with a scan address assigned to each register of the device A method in which a fault is generated by scanning in the specified register by specifying. This method is called a one-shot scan-in method because it scans into one designated register. In this type of system, the scan address from the program and the point of failure (the address comparison address specified by the program,
For example, there is JP-B-58-33579 as an example devised so that it can be set when micro-instruction addresses match.

[Problems to be solved by the invention]

In the above method (1), since the parity bit is forcibly inverted and a parity error is generated, a parity error occurs everywhere in the apparatus, and the re-execution function cannot be confirmed. In the above method (2), since the master check is set to 1, some confirmation of the re-execution function can be obtained, but since the original check latch is not lit, detailed verification of the failure processing cannot be performed. There is a disadvantage that the verification from the failure detection mechanism (eg, parity check circuit) to the master check latch cannot be performed.

In the above method (3), the fault verification can be performed by using any general check latch or general data latch, but the panel and service processor must manually set the values required for the fault verification. There is a problem that it takes a lot of time and effort to verify a failure, and the reproducibility of failure verification is poor.

In the above method (4), the program can set the data necessary for the pseudo fault occurrence by a special instruction, so that the test combination with the general instruction can be easily performed. However, the scan-in time for causing the fault can be increased. Since the latch is set to 1 completely asynchronously with the normal logic operation timing, even if a failure occurs in the specified latch due to the time relationship between the logic operation timing and the scan-in signal, a failure detection circuit other than the expected failure detection circuit There is a problem that a failure is detected and the expected re-execution result cannot be obtained.

FIG. 5 (a) is a logical configuration diagram for explaining the problems of the conventional one-shot scan. The configuration is duplicated random access memory (RAM50, RAM51) and output register A0R52, A1R53 of the random access memory and selector circuit SEL54 and register to which SEL54 output signal is connected.
It consists of BR55 and each register has parity check circuit 56
And a check latch (ER0A57, ER1A58, ERB59).

Also, the input select signal of the selector circuit 54 is a register
Controlled by the output signal of parity check 56 of A0R52, register A1R when a parity error is detected in register A0R
53 Select output.

When injecting a pseudo fault into a value that causes a parity error with a one-shot scan signal (OSSIT in the figure) for one bit in register A0R52, a test to see if duplication logic operates normally in this configuration is performed. , The expected check latch is only ER0A57, but if the OSSIT signal changes between the update timing T0 of register A0R52 and the update timing T2 of BR55, as shown in the time chart of FIG. A pseudo obstacle is transmitted to BR55, and the check latch ERB lights up. Therefore, there is a problem that the expected failure processing result cannot be obtained.

As another problem, when performing a failure test in a system including a plurality of processing devices, (1) a place that can be commonly used by each processing device, and (2) a place that is affected by a request signal input from another processing device. The failure test has a problem that the failure processing expectation is erroneous because it detects a failure when a pseudo failure created by the failure test side processing is accessed from another device. Examples of the location of (1) above include a KEY storage in the main memory control unit of the diadec processing device, and examples of (2) include locations affected by a buffer storage device cancel request from another processing device. This is because, in a system that uses the main storage device in common and has a buffer storage device that is a copy of the main storage device in each processing device, when a store operation occurs from one processing device, the buffer in another processing device is Since it is necessary to check whether or not the contents rewritten by the store operation are stored in the storage device and cancel if there is any, a failure occurs due to a request from another processing device.

An object of the present invention is to solve the above conventional problems, and in an information processing apparatus having a self-diagnosis / recovery function, information that can be normally processed in a trouble process and a re-execution function can be verified without manpower. It is to provide a pseudo failure generation method for a processing device.

[Means for solving problems]

In order to solve the above problems, the pseudo failure generation method of an information processing apparatus of the present invention includes one or a plurality of information processing apparatuses each having a self-diagnosis / recovery means of the apparatus, and each information processing apparatus is usually provided with The scan-in means for addressing and setting and resetting the internal register of the apparatus completely independently of the operation control circuit of the device, and the means for setting the information necessary for the scan-in means to start the operation by a special instruction. In the system, each information processing device sets or resets the register addressed by the above instruction in synchronism with the register use timing, completely independently of the state of the normal operation control circuit, and during general instruction processing executed later. A pseudo-fault, and when performing a fault test on an access location that is commonly used by multiple information processing devices, a pseudo-fault was attempted. Is characterized from the point until the detected pseudo fault, the access from the information processing apparatus other than the information processing apparatus managed a dummy failure to common access location be frozen.

[Action]

In the present invention, since the signal for generating the pseudo fault and the scan-in signal operate in synchronization with the operation timing for updating the latch and the register in the normal logic operation,
Even if the normal logic operation and the scan-in signal are issued at the same time, a pseudo fault can be created in the register designated by the program, and the intended fault detection mechanism can be verified. Further, a failure test at a common location from a plurality of processing devices can be performed without being aware of other processing devices.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a pseudo failure generation system of an information processing apparatus showing an embodiment of the present invention.

In FIG. 1, a control memory 2 is a memory for storing a microprogram, which is accessed by the microinstruction address register 1 and the read data is set in the microinstruction register 3. The address comparison register 4, the scan address register 6, and the scan-in data register 7 mean that data can be set in the above three registers by a special instruction from the program through the set data line 20. .

The scan control unit 8 is a control unit that controls the normal scan-in and scan-out such as logout, and outputs various signals. Here, the scan-in signal 23 and the scan-in data line 24 are shown. In this embodiment, the contents of the microinstruction address register 1 and the address comparison register 4 are compared by the address comparison circuit 5, and the output thereof is ORed by the OR line 9a, and the scan-in data interface line 25 is supplied to the scan-in signal synchronization circuit 11. Sent out. In addition, the output line 22 of the scan-in data register 7
Is ORed by the OR circuit 9b and is sent to each part of the apparatus as the scan-in data interface line 26. Similarly, the output line 21 of the scan address register 6 is also sent to each part of the apparatus.

On the receiving side, the contents of the scan address register output line 21 are decoded by the scan address decoding circuit 10 in order to obtain the scan address previously assigned to each register of the device, and the corresponding flip-flop address 27
To produce. Also scan-in data interface line
25 is synchronized by the scan-in signal synchronizing circuit 11 so as to match the timing of each register on the receiving side. Flip-flop 14 is timing during normal operation
The data line 28 is set and used at T0. At the time of scan-in, the value specified by the address line 27, the scan-in data interface line 26, and the output line of the scan-in signal synchronization circuit 11 which designates the contrast flip-flop is transferred to the flip-flop 14 through the AND circuit 12 and the NOT circuit 13. Connected.

Next, the operation mode when a pseudo fault is generated will be described. A special instruction such as a diagnostic instruction that expresses the location (scan address) where you want to generate a pseudo fault from the program, the value (scan-in data) that you want to generate a pseudo fault, and the value when you want to generate a fault (eye-closure instruction compare address). Are set in the scan address register 6, the scan-in data register 7, and the address comparison register 4. After making the following preparations, move on to the test program.
When the pseudo fault occurrence setting time comes, the comparison between the microinstruction address register 1 and the address comparison register 4 is made by the comparison circuit 5.
The output is detected by the OR circuit 9a, and the output is ORed with the normal scan signal by the OR circuit 9a, and then distributed to each part of the apparatus. On the other hand, the scan address register 6 is decoded by the decode circuit 10 and the target flip-flop is designated. The flip-flop 14 designated by the decoding circuit 10 is forced to perform scan-in in synchronization with the flip-flop timing while executing the normal operation, and is in the same state as the apparently intermittent failure. make. After that, fault processing and re-execution are performed based on the function of the device, and the normality of the device can be verified.

FIG. 2 is a diagram showing an example of a synchronized scan-in to a flip-flop in which the same logic as in the broken line 100 in FIG. 1 is represented by another method.

The normal logic timing and the synchronization at the scan-in are performed by using the same timing at the scan-in.

FIG. 3 is a diagram showing an example of a system configuration of an apparatus provided with a necessary function for testing a place commonly usable by a plurality of processing apparatuses.

This system is composed of two processing devices 30, a main storage device control unit (hereinafter referred to as SC) 34 that receives a request request issued from the processing device 30, and a main storage device 36. Has an SC freeze latch 31 for instructing freezing of a request request from another processing device to the SC 34.

Further, the SC 34 has an SC request request control unit 35, and the request request signal 32 and the other device request request freeze instruction line 33 are connected to the control unit 35 from each processing device 30.

An example of the operation necessary for recognizing the faulty function of the common unit on the processing device will be described based on the common unit test flow chart of FIG. One processor can run a general instruction test program other than the failure function test program while the common function test program is being executed by one processor, so that two processors can be tested independently. Good for improving equipment test efficiency. However, in the present embodiment, in order to prevent the pseudo-fault issued from the processing unit on the fault function test program processing side from being detected by the processing unit on the general instruction execution side, the processing unit on the fault function processing side is shown in FIG. Set up and execute the program in the procedure (step). Here, during a step, * means a special command.

First, execute the SC freeze start command. When this instruction is executed, the set SC freeze signal (SSCFLZ) is output to the SC freeze latch 31 in the processing device 30 to set the latch 31 (step 401). Next, the scan-in information setting instruction is executed to set the information value necessary for causing the pseudo-in on scan-in (step 402). Next, the general test instruction is executed according to the information set in step 402 (step 403). A failure occurs during execution of this instruction. Then, the SC freeze cancel instruction outputs a reset freeze signal (RSCFLZ) and resets the latch 31 set in step 401 (step 404).

The SC request request control unit 35 in the SC 34 requests the request from another processing device while the SC freeze latch 31 is "1".
By freezing 32, it becomes possible to give priority to the request request 32 from the own processing device, and the expected pseudo fault can be generated in the processing device on the expected side.

〔The invention's effect〕

As described above, according to the present invention, in the information processing device having the self-diagnosis / recovery function, the failure processing and the verification of the re-execution function, which are normally difficult to verify, can be performed reliably, more completely, and in a shorter time. It is possible without manpower.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a scan-in pseudo failure generation system showing an embodiment of the present invention, and FIG. 2 is a configuration diagram of a scan-in synchronization system to a target flip-flop showing another embodiment of the present invention. FIG. 3 is a system configuration diagram of an apparatus having a function necessary for performing a failure test on a place commonly usable by a plurality of processing apparatuses, FIG. 4 is a test flow chart of a common unit shown in FIG. 3, and FIG. FIG. 1 is an overall configuration diagram of a conventional scan-in pseudo failure generation method. 1: Micro instruction address register, 4: Address comparison register, 5: Address comparison circuit, 6: Scan address register, 7: Scan-in data register, 10: Scan address decoding circuit, 11: Scan-in signal synchronization circuit, 14:
Target flip-flop, 30: processing device, 31: SC freeze latch, 34: main memory control unit, 35: SC request request control unit, 36: main memory, 51, 53: general register.

Claims (1)

[Claims] 1. A system comprising one or a plurality of information processing devices having self-diagnosis / recovery means for the devices, wherein each information processing device has a register inside the device completely independent of a normal operation control circuit. Each of the information processing devices is provided with a scan-in means and an address holding means for designating the address of and the setting / resetting of the register, and a means for setting information to the scan-in means and the address holding means by a special instruction. Based on the time when the microinstruction address and the information in the address holding means match, the register addressed by the scan-in means is synchronized with the register designation timing completely independently of the state of the normal operation control circuit. Set or reset specified by the scan-in means to generate a pseudo-failure during the processing of a general instruction executed later. And each information processing device
When performing a failure test on an access location that is commonly used by multiple information processing devices, access to the common access location from other information processing devices from the time when the pseudo failure is about to be detected A pseudo fault occurrence method for an information processing apparatus, characterized in that it is provided with means for issuing a freeze instruction.