JPS6049454A - Main memory device - Google Patents

Abstract

PURPOSE:To attain a resetting action of a pseudo fault generating means and a recovering action of a memory part in a single memory cycle, by using the pseudo fault generating means, a write data supply means, a memory part recovering means and an address selecting means. CONSTITUTION:When a psendo fault reset signal 132 is supplied to a pseudo fault generating register 133 and a memory part recovering means 140, the register 133 is reset and a write action start signal 149 is delivered to start the write action. An address selecting signal 150 is delivered when a psoudo fault is reset. Thus the writing is carried out to the address which is latched to the register 313. In this case, the address of a memory part 110 which produces pseudo fault is latched by the register 313. Therefore the contents of the part 110 are recovered by a reset action of the pseudo fault. The recovery action of the part 110 is possible in a single memory cycle since the pseudo fault is reset in a single memory cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a main storage device, and more particularly to a reset method for a pseudo fault occurring in a storage section.

■ Explanation of the prior art The main storage device has an 8EC/
DED (Single Brrror Correct
iorVDouble Error Detection
) It is normal to have a function. The 8Ec/D
The BD function test is performed by generating data containing 2- at a certain address in the storage section, and then checking whether 8EC/DED of the 2- data is performed in a read operation. The process of generating data containing the data in the storage unit and the so-called pseudo failure of the storage unit are normally performed as follows.

First, a pseudo-failure generating means is set to instruct generation of a pseudo-fault, and then a write operation is performed with arbitrary data to an address at which a pseudo-fault is to be caused. At this time, the data written to the storage section becomes so-called error data in which the hamming bits do not match because the pseudo failure generating means is set.

In order to reset the pseudo fault set as above, after resetting the pseudo fault generation means, a write operation is required to restore the information at the address in the storage unit that caused the pseudo fault. In a conventional main memory device, each of the former and latter operations requires one memory cycle, so it has the disadvantage that resetting a pseudo failure is troublesome.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology.Therefore, an object of the present invention is to make it possible to reset the pseudo-failure generation means and repair the storage unit in one memory cycle. The object of the present invention is to provide a new main storage device that has improved performance.

(4) Structure of the invention In order to achieve the above object, the main storage device according to the present invention comprises:
A pseudo-fault generating means that can be set and reset by a pseudo-fault set/reset operation request from a connected device such as a central processing unit, and a write data supply that supplies write data and check information to a specified address in the storage unit. and an address that is sent along with a malfunction request when a write operation request is received from the connected device after the pseudo fault generating means is set, and when a pseudo fault reset operation request is received from the connected device. address selection means for supplying the stored address to the storage unit and supplying the address from the connected device to the storage unit except for a request for a pseudo-failure reset operation; and when a write operation request is received from the connected device The write data and check information supplied to the storage unit by the write data supply means are made to be in a consistent state when the pseudo failure generating means is in a reset state, and are made to be in a mismatched state when the pseudo failure generating means is in a set state. instruct,
The apparatus further includes a storage unit repairing means for starting a write operation to the address held in the address supplying means when a pseudo-failure reset operation request is received from the connected device.

(5) Detailed Description of the Invention Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a main memory device according to the present invention. In the figure, reference number 110 is a storage unit for storing information, and 120 is write data 121 and humming bits 12 as information stored in the storage unit 110.
Write 2 to data register 123 and Hamming register 1
130 is a pseudo fault generation means having a pseudo fault generation register 133 which can be set/reset by a set signal 1314 and a reset signal 132; 140 is a write data supply means for supplying write data through the write operation instruction signal 141 and the reset signal 132; Signal 132 and pseudo failure register 13
3 and input the output signal from AND gates 142 to 14.
4. The write data register 123 and the Hamming register 12 are
3, an address register 313 that latches the address signal 311 in response to the set signal 312;
The address selection means includes an AND gate 314 that generates the set signal 312 and an address selection circuit 315 that selects one of the address signal 311 and the output of the address register 313. Storage unit 1 based on Figure 1.
The setting and resetting operations of pseudo faults for No. 10 will be described below.

A pseudo fault is set for the storage unit 110 as follows.

(2) Write arbitrary data (1st data) to the address in the storage unit 110 where you want to cause a pseudo failure.

(2) Set the pseudo-failure occurrence register 133.

(2) Write the 2nd data to the same address as the 1st data.

In the above-mentioned operation (2), the write data 121 of the 1st data is added to the write data register 123 by 2 and written to the storage section 110. On the other hand, the Hamming bit 122 of the 1st data generated based on the write data 121 is latched in the Hamming register 124 and also in the storage unit 110.
written to. Note that the latching operations for the write data register 123 and the Hamming bit register 124 are performed by set signals 147 and 148, respectively, and once the information is latched, it is not updated until the next set signal arrives.

Next, when the pseudo-failure occurrence register 133 is set in the operation (2) above, even if there is a write operation instruction signal 141 during the write operation, the AND circuits 143 to 144 cause the set signal 1 to be set.
48 is not output.

Finally, in the operation of 0, a write operation is performed at the same address as 2 with 2nd data that differs by at least one bit from the 1st data. Due to this operation, the write data 121 of the 2nd data is written to the write data register 12.
31C is latched and written to the storage section 110. on the other hand,
The Hamming register 124 is a pseudo failure register 133
Since the set signal 148 is not outputted, it is not updated.

Therefore, the Hamming bit generated by the first data remains in the Hamming register 124, and the Hamming bit is written into the storage unit 110 again.

Due to the above-described operation, so-called error data, in which the data and the Hamming bit do not match, is written in the storage unit 110. The operation of the address selector R310 in the write operations (2) and (2) above is as follows.

Since the address selection signal 150 is not output during the operation (2), that is, when the pseudo failure register 133 is not set, the address selection circuit 315 selects the address signal 311 and supplies it to the storage section 110.

During the operation (2) above, that is, when a write operation request is received from the connected device after the pseudo-failure occurrence register 133 is set, the output of the pseudo-failure occurrence register 133 and the write operation instruction signal 141 are output to the AND gate 314. A set signal 312 is output. The address signal 311 is latched into the address register 313 by the set signal 312. However, since the address selection signal 150 is not output, the address signal 311 is supplied to the storage section 110, and a write operation is performed to the address.

Next, I will explain about the pseudo-disability Nori Nanatsu).

When a pseudo fault reset operation is instructed from a connected device such as a central geographic device, a reset signal 1°32 is input to the pseudo fault occurrence register 133, and the register is reset.

Further, the reset signal 132 is inputted to the storage section repair means 140, which outputs a write operation start signal 149 through the AND gate 142 → register 146 → OR gate 145 → AND gate 144, and starts the write operation. . At the same time, set signals 147 and 148 are also output, so write data 121 and Hamming bit 122 are taken into write data register 123 and Hamming register 124, and information to be written to storage unit 110 during the write operation. used as.

Since the address selection signal 150 is output during the pseudo-failure reset operation described above, the address latched in the address register 313 is supplied as the address to the storage section 110.

As a result, the write operation activated during the pseudo fault reset operation is performed on the address latched in the address register 313. address register 3
13 contains the address of the memory 5llO in which the pseudo fault has occurred, so the contents of the memory section are restored by the reset operation of the pseudo fault.

FIG. 2 is a time chart showing the operation of FIG. 1. In FIG. 2, the 1st to 3'rd memory cycles correspond to a pseudo failure setting operation, and the 4th memory cycle corresponds to a pseudo failure reset operation.

In the following description of FIG. 2, it is assumed that the generation of Hamming bits, which are written together with data in the storage section when a write operation is requested from a connected device, is performed within the main storage device.

In FIG. 2, the 1st memory cycle shows a case where a write operation request for data D1 to address AI is received from a connected device. When this operation is instructed, set signals 147 and 148 are outputted by the 1'' write operation instruction signal 141, and the write data D1 and the humming bit H1 generated by the data are sent to the write data register 123 and the humming register 124, respectively. 2. Further, a write operation start signal 149 is output, a write operation cycle is started by this signal, and the write data D is sent to the address person 1 of the storage section 110.
1 and Hamming bit H1 are written.

The 2nd memory cycle shows a case where a pseudo failure set operation request is received from the connected device. When this operation is instructed, the pseudo fault occurrence register 133 is activated by the set signal 131.
is set.

The 3rd memory cycle shows a case where a request for writing data D2 to address A1 is received from a connected device. Since this operation causes a pseudo failure to occur, data D2 must be different from D1 by at least one bit. For example, if you want to generate a pseudo failure of 1 bit error, use data obtained by inverting any 1 bit of Dl as D2, and if you want to generate a pseudo failure of 2 bit errors, use the data obtained by inverting any 2 bits of Dl. Used as D2. When the action is instructed,
A set signal 147 is output in response to the write operation instruction signal 141, and the write data D2 is latched into the write data register 123. On the other hand, the set signal 148 is not outputted by the pseudo fault occurrence register 133, and the Hamming register 124 is not updated. As a result,
Write data D2 is written to address A1 of storage unit 110 in a write operation cycle activated by write operation activation signal 149.
and Hamming bit H1 is written. Therefore, storage unit 1
This means that newly released error information in which the data and the Hamming bit do not match has been written in No. 10. At this time, the address A1 is latched into the address register 313 by the number 1 312.

The 4th memory cycle indicates a case where a pseudo fault reset operation request with data D3 is received from the connected device. When this operation is instructed, the pseudo fault occurrence register 133 is reset by the reset signal 132, and Set signals 147 and 148 are output.

The set signals 147 and 148 double the e write data D3 and the Hamming bit H3 into the write data register 123 and the Hamming register 124, respectively. Also, since the write operation activation signal 149 and the address Yuzawa (i number 150) are output, the write operation for the address A1 is activated by the cough signal. As a result, the address A1 of the storage section 110
The write data D3 and the humming pitch l-H3 generated by D3 are written to the 1st to 3rd
The contents of the storage unit that caused the pseudo failure in the rd memory cycle will be repaired in the 4th memory cycle.

(41) Detailed Description of the Invention As explained above, the present invention has the advantage that the reset of the pseudo failure generating means and the repair operation of the storage section can be performed in one memory cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a diagram for explaining the operation of FIG. 1. 110... Storage unit, 120... Write data supply means, 121... Write data, 122... Hamming bit, 123... Write data register, 124... Hamming register, 130... ...Pseudo fault generation means, 13
1...Set signal, 132...Reset signal, 13
3...Pseudo-failure occurrence register, 140...Storage unit repair means, 141...Write operation instruction signal, 142゜1
43, 144...AND gate, 145...OR gate, 146...Register, 147.148...
・Set signal, 149...Write operation start signal, 150
... address selection signal, 310 ... address selection means, 311 ... address signal, 312 ... set signal, 313 ... address register, 314 ... logical product), 315 ... address Selection circuit patent applicant
NEC Corporation Representative Patent Attorney Yutabe Kumagai

Claims (1)

[Claims] In a main storage device that stores data and check information generated by the data at an address within the storage section specified by a write operation request from a connected device such as a central processing unit, a pseudo fault set/reset from the connected device is performed. pseudo fault generating means that can be set and reset by an operation request; write data supply means for supplying write data and check information to a specified address in the storage unit; and after the pseudo fault generating means is set. When a write operation request is received from the connected device, the address sent along with the malfunction request is held, and only when a pseudo failure reset operation request is received from the connected device, the held address is stored in the storage unit. Address selection means supplies an address from the connected device to the storage unit except for a request for a pseudo-failure reset operation, and when a write operation request is received from the connected device, a means for instructing the write data supply means to bring the write data and check information supplied to the storage unit into a consistent state, while instructing the write data supply means to bring them into an inconsistent state when they are in a set state; 2. A main memory device comprising: a storage unit repair unit for starting a write operation to an address held in the address supply unit when a pseudo-failure reset operation request is received from the connected device.