JPH01169640A - Pseudo trouble generating system for information processor - Google Patents

Abstract

PURPOSE:To attain the trouble processing which is hard to verify and the verification of a re-executing function without any labor by freezing the access from an information processor except the information processor to generate the pseudo trouble to a common access place until the pseudo trouble is detected from when the pseudo trouble is generated. CONSTITUTION:An SC request demand control part 35 in a main memory control unit SC34 freezes a request demand 32 from other processor while an SC freezing latch 31 is '1', can give a priority to the request 32 from a self- processor and the expected pseudo trouble can be generated at the processor at the side to expect. Namely, a signal to generate the pseudo trouble, namely, a scanning-in signal is synchronized with the action timing to update the latched register with an ordinary logical action and operated. Thus, even when the ordinary logical action and the scanning-in signal are simultaneously issued, the pseudo trouble can be generated at the register designated by the program and the intentional trouble detecting mechanism can be verified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for generating a simulated failure, and particularly to a method for generating a simulated failure for an information processing apparatus having self-diagnosis and recovery functions.

[Conventional technology]

Before shipping an information processing device, it is necessary to inspect and confirm the normality of all its functions.
It is difficult to test the malfunction detection mechanism, especially the re-execution function. That is, since the device is of course designed so as not to malfunction under normal conditions, the normality of the detection mechanism cannot normally be verified. Furthermore, since the re-execution function assumes intermittent malfunctions, it becomes increasingly difficult to verify.

Conventionally, there are the following failure generation methods for verifying the malfunction detection mechanism and re-execution function of a device.

(1) Reverse parity method A method that forcibly inverts the parity bit and causes a failure.

(2) Master check method A method in which the master check output, which is a collection of check clutches, is set to 1 to generate a failure.

(3) Specify the address conveyor address and the latch you want to cause a failure from the error in-jet system panel or service processor, and when the microinstruction address or instruction address and address conveyor address match, force the latch specified above. A method of lighting up.

(4) Scanning means provided for setting initial information and logging out of the one-shot scan-in type processing device.

In particular, this method uses the scan-in function to specify a 1-bit register with the scan address assigned to each register in the device, and scans in the specified register to cause a failure.

This method is called a one-shot 1-scan-in method because it scans into a specified register. An example of this type of method that allows the program to set the scan address and the time point at which a failure occurs (when the address comparison address specified by the program matches the microinstruction address, for example) is
-33579, etc.

[Problem that the invention seeks to solve]

The method (1) above forcibly inverts the parity pits and generates parity errors, so parity errors occur everywhere in the device, and the re-execution function cannot be confirmed. In method (2) above, since the master check is set to 1, it is possible to confirm the re-execution function to a certain extent, but since the original check clutch is not lit, detailed verification of failure handling cannot be performed. There is also the disadvantage that verification from the fault detection mechanism (eg, parity check circuit) to the master check clutch cannot be performed.

The above method (3) allows fault verification using any general check latch or general data latch, but the values necessary for fault verification must be manually set from the panel or service processor. There are problems in that fault verification requires a great deal of time and effort, and fault verification has poor reproducibility.

The method (4) above allows you to set the data necessary for pseudo-failure generation using special instructions from the program, making it easy to combine with general instructions. Since the latch is set to 1 completely asynchronously with the normal logic operation timing, even if a failure occurs in the specified latch due to the time relationship between the logic operation timing and the scan-in signal, failures other than the expected failure detection circuit will be detected. There are cases where a fault is detected in the circuit, and there is a problem that the expected re-execution result cannot be obtained.

FIG. 5(a) shows a logical configuration diagram for explaining the problems of the conventional one-shot 1-scan. Its configuration consists of duplicated random access memory (RAM50.
51) and random access memory output register AOR
52, AlR53 and selector circuit 5EL54 and 5EL
It consists of a register BR55 to which 54 output signals are connected,
Each register is equipped with a parity check circuit 56 and a check clutch (EROA57, ERIA58, ERB59).

Further, the input select signal of the selector circuit 54 is controlled by the output signal of the parity check 56 of the register AOR52, and when a parity error is detected by the register AOR, the output of the register AlR53 is selected.

Test 1 to see if the duplex logic operates normally in this configuration
When ~ is executed by injecting a pseudo fault into a value that causes a parity error by using a one-shot scan signal (○5SIT in the figure) for a certain pin in register AOR52, the expected check clutch is only EROA57. , as shown in the time chart of FIG. 5(b), the 08SIT signal corresponds to the update timing To and BR5 of register 80R52.
If the change occurs during the update timing T2 of 5, the pseudo failure of register 80R52 will be transferred to BR55, and the check clutch FRB will light up. Therefore, there was a problem that the expected failure processing result could not be obtained.

Another problem is that when performing a failure test on a system consisting of multiple processing devices, (1) a location that can be commonly used by each processing device, and (2) a location that can be used commonly by each processing device;
Fault testing for locations affected by signals has the problem of erroneous expectations for fault handling because the fault is detected when a pseudo fault initiated by the processing on the fault testing side is accessed from another device. The location of the above ('') is the K in the main memory control section of the Diadec processing unit.
Examples include EY storage 1 to storage, and (2) includes locations that are affected by buffer storage device cancellation requests from other processing devices. This is because in a system that uses the main memory in common and has a buffer memory in each processor that is a copy of the main memory, when a store operation occurs from one processor, the buffer in the other processor Since it is necessary to check whether or not there is content rewritten in the storage device by the S1-A operation, and to cancel it if there is, a failure may occur due to a request from another processing device.

The purpose of the present invention is to solve such conventional problems and to provide information that allows verification of fault handling and re-execution functions, which are normally difficult to verify, without human intervention in information processing devices that have self-diagnosis and recovery functions. An object of the present invention is to provide a method for generating a pseudo failure in a processing device.

[Means for solving problems]

In order to solve the above problems, the pseudo-failure generation method for information processing equipment of the present invention includes one or more information processing equipment having device self-diagnosis/recovery means, and each information processing equipment has a scan-in means for addressing and setting and resetting registers inside the device completely independently of the operation control circuit of the device; and means for setting information necessary for the scan-in means to start operation by a special instruction. In the shear system, each information processing device sets or registers the register addressed by the above instruction in synchronization with the register use timing, completely independent of the state of the normal operation control circuit, and sets or resets the register addressed by the above instruction to the register 1 to be executed later. When generating a pseudo failure during instruction processing and performing a failure test on an access location commonly used by multiple information processing devices,
A feature of this method is that access to the common access location from information processing devices other than the information processing device that caused the pseudo-failure is frozen from the time the pseudo-fault is caused until the pseudo-fault is detected.

[Effect]

In the present invention, the signal for generating a pseudo fault, the scan-in signal, is a normal logic operation and operates in synchronization with the operation timing for updating latches and registers.
Even if a normal logic operation and a scan-in signal are issued at the same time, a pseudo fault can be created in a register specified by the program, allowing verification of the intended fault detection mechanism. Furthermore, failure testing at a common location from multiple processing devices can be performed without being aware of other processing devices.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an overall configuration diagram of a pseudo-failure generation method for an information processing apparatus showing an embodiment of the present invention.

In FIG. 1, a control memory 2 is a memory that stores a microprogram, and is accessed by a microinstruction address register 1, and read data is set in a microinstruction register 3. Address comparison register 4. The scan address register 6 and the scan-in data register 7 mean that data can be set in the three registers by a special command from a program via the set data line 20.

The scan control unit 8 is a control unit that controls normal scan-in and scan-out operations such as logout, and outputs various signals, but here the scan-in signal 23.
A scan-in data line 24 is shown. In this embodiment, the contents of the microinstruction address register 1 and the address comparison register 4 are compared by the address comparison circuit 5, and the output thereof is ORed by the OR circuit 9a, and is connected to the scan-in signal synchronization circuit 11 as the scan-in data interface line 25.
sent to. Further, the output line 22 of the scan-in data register 7 is ORed by the OR circuit 9b, and sent out as the scan-in data interface line 26 to each part of the apparatus. Similarly, the output line 21 of the scan address register 6
It is also sent to each part of the device.

On the receiving side, the contents of the scan address register output line 2J are decoded by the scan address decoding circuit 10 to generate the corresponding flip-flop address 27 in order to decode the scan addresses previously assigned to each register of the device.

Further, the scan-in data interface line 25 is synchronized by a scan-in signal synchronization circuit ↑1 so that it can be synchronized with each timing of each register on the receiving side. During normal operation, the flip-flop 14 is used to connect the data line 28 at timing To. During scan-in, the address line 27. specifies the target flip-flop. Scan-in data interface line 26. And the value specified by the scan-in signal synchronization circuit 11 output line is the AND circuit 12. It is connected to a flip-flop 14 through a knot circuit 13.

Next, we will discuss the operation mode when generating a pseudo failure. A value expressing the location where you want to cause a pseudo fault (scan address), the value where you want to make the pseudo fault (scan-in data), and the point in time where you want the fault to occur (micro-command conveyor address) from the program is sent using a special instruction 2, for example, a diagnostic command. Then, the scan address register 6, scan-in data register 7, and address comparison register 4 are loaded. After the preparations described below, the test program will begin running.

When the pseudo-failure generation setting point is reached, the microinstruction address 1
A match between the register 1- and the register 4 of the address comparison 1 is detected by the comparison circuit 5, and the output thereof is ORed with the normal scan signal by the OR circuit 9a, and then distributed to each -11= section of the device. On the other hand, the scan address register 6 is
It is decoded by the decoding circuit 10, and the target flip-flop is designated. The flip-flop 14 designated by this decoding circuit 10 was forcibly scanned in synchronization with the flip-flop timing even though it was performing normal operation, and there appeared to be an intermittent failure. create the same state. Thereafter, failure handling and re-execution are performed based on the functions of the device, making it possible to verify the normality of the device.

FIG. 2 is a diagram illustrating an example of a synchronized scan-in to a flip-flop, with logic similar to that within dashed line 100 of FIG. 1, but alternatively represented.

Synchronization between logic timing and scan-in is normally achieved by using the same timing during scan-in.

FIG. 3 is a diagram showing an example of a system configuration of a device equipped with necessary functions for testing a location that can be commonly used by a plurality of processing devices.

This system consists of two processing devices 30. This processing equipment [30
It is composed of main storage device control units 1 to 34 (hereinafter referred to as SC) and a main storage device 36, which receive requests issued from other processing devices. It has an SC freeze latch 31 that instructs freezing.

Further, the 5C 34 includes an SC request request control section 35, and the request request control section 35 receives request request signals 32. Request for other equipment is required. Unfrozen indication line 33
is connected.

An example of the operation required to recognize a faulty function in the common section of the processing device 2 will be explained based on the common section test flow diagram of FIG. The ability of one processing device to run a general command test program other than the faulty function test program while one processing device is running the faulty function test program for the common section means that the test 1-1 of the two processing devices can be performed independently. is possible,
Good for improving equipment testing efficiency. However, in this example,
In order to prevent the processing device on the general instruction execution side from detecting a pseudo fault issued by the processing device on the faulty function test program processing side, the processing device on the faulty function processing side executes the program according to the procedure (steps) shown in Figure 4. Assemble and execute. Here, * in the step means a special command.

First, an SC freeze start command is executed. When this command is executed, a set SC freeze signal (SSCFLZ) is output to the SC free latch 31 in the processing device 30 to set the latch 31 (step 401).

Next, a scan-in information setting command is executed to set information values necessary to generate a pseudo failure by scan-in (step 402). Next, general test 1 - execute the instruction using the information set in step 402 (step 40
3). A failure occurs during the execution of this instruction. Then, S
The C-freeze release command is a reset 1-freeze signal (R8
CFLZ) and resets the latch 31 that was closed in step 40 (step 404).

The SCC refrigeration unit 1 to the request control unit 35 in the 5C34 freezes requests 32 from other processing devices while the SC freeze latch 3 is “4” and gives priority to requests 32 from its own processing device. This makes it possible to generate an expected pseudo-failure in the processing device on the expected side.

〔Effect of the invention〕

As explained above, according to the present invention, in an information processing device having a self-diagnosis/recovery function, failure handling and re-execution functions, which are normally difficult to verify, can be verified more reliably, more completely, and in a shorter time. This can be done without any human effort.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a scan-in pseudo failure generation method showing one embodiment of the present invention. FIG. 2 is a configuration diagram of a scan-in synchronization method for a target flip-flop showing another embodiment of the invention. Figure 3 is a system configuration diagram of a device that has the functions necessary for fault testing a commonly usable location from multiple processing devices, and Figure 4 is a test I of the common part shown in Figure 3.
- Flowchart FIG. 5 is an overall configuration diagram of a conventional scan-in pseudo failure generation method. 1-2 Microinstruction address register, 4 Near address comparison register, 5 Near address comparison circuit, 6: Scanner I
Address register, 7: Scan-in data register, 1
0 Niscan address decoding circuit, 11 Niscan-in signal synchronization circuit, 14: Target flip-flop, 30:
Processing device, 31: SC freeze latch, 34: Main storage control unit, 35: SC request request control unit, 3
6 two main memories, 51 and 53 general registers. 16-timing RMO output data 5SIT OR ROA R RB TOTI T2 T3 To Tl-9Q-

Claims (1)

[Claims] 1. Equipped with one or more information processing devices that have device self-diagnosis and recovery means, and each information processing device has internal registers that are addressed and set completely independently of the normal operation control circuit. , in a system equipped with scan-in means for resetting, and means for setting information necessary for the scan-in means to start operation by a special instruction, each information processing device normally stores the register addressed by the above-mentioned instruction. It is set or reset in synchronization with the register usage timing, completely independent of the state of the operation control circuit of When performing a fault test for an access location that is connected to a common access location, freezing access to the common access location from information processing equipment other than the information processing equipment that caused the pseudo-failure from the time a pseudo-fault is initiated until the pseudo-failure is detected. A pseudo-failure generation method for an information processing device characterized by: