JPH01297746A - Memory diagnosing system - Google Patents

Abstract

PURPOSE:To find a mutual intervention error by which the specific bit of each memory cell is fixed by writing data shifted sequentially by a shift means, then, reading them out and comparing with each other afterward. CONSTITUTION:The write of the data to be diagnosed is started after a request 101 from a processor side is set at a request accepting FF12, a write memory diagnosing request at a request code register 13 from a request code 102, the initial value of an address from an address 103 to an acceptance register 14, and the data to be diagnosed at an acceptance data register 15 from the data 104. The initial address of the register 14 is stepped by a stepping counter 17 sequentially, then, becomes the write address of the memory 2, and the data to be diagnosed is shifted by a shifter 19 sequentially, then, becomes the write data. After the write being completed, the write data is read in a read register 23 sequentially from the memory 2, and is compared with the data in a write register 22 which stores the write data shifted by the shifter 19 by a comparator 24.

Description

TECHNICAL FIELD The present invention relates to a memory diagnostic method, and more particularly to a memory diagnostic method in a system control device that controls writing and reading of data to and from a memory.

Prior Art Conventionally, in this type of system control device, specific write data is written to multiple locations in memory using addresses supplied from a circuit that counts up memory addresses, and after writing of the write data is completed, the data is is read from the memory, and a match check is performed between the read data and the written write data. This memory checking system is described in detail in the invention published in Japanese Patent Publication No. 1720/1983.

In a memory, a mutual interference error may occur between memory cells constituting the memory, such as a specific bit of data in each memory cell being fixed to "0" or "1".

Even if the same data pattern is written into memory and checked in order to detect mutual interference errors, it is difficult to detect mutual interference errors.

In such conventional system control devices, a specific line 1
This method has the disadvantage that it is difficult to detect mutual interference errors because the data is written into the memory and the write data is checked for coincidence with the data written from the memory.

Furthermore, even if this system control device writes different data patterns to the memory and attempts to check them, it is necessary to output the number of different data patterns and the riff varnishes 1 to 1, and the processing device that outputs the riff varnishes 1 to The disadvantage is that the burden increases.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional method, and it is possible to easily discover mutual interference errors and reduce the burden on the processing device that outputs the rift varnish l-. Assume that Proposition 1 (of the proposed memory diagnostic method) is [1].

Structure of the Invention The memory diagnostic method according to the present invention includes a request l~holding means for holding a ref varnish from a diagnostic device to a memory, and a ref varnish 1~ held by the request l~holding means.
address supplying means that sequentially advances predetermined addresses from the diagnostic device and supplies them to the memory, and predetermined data from the diagnostic device using Shift 1 to means for sequentially shifting to Shift 1, and the shift 1 to means perform shift 1 to the address supplied from the address supply means in response to a write request from the diagnostic device held in the holding means to the rift varnish 1. After writing the predetermined data stored in . The present invention is characterized in that the memory is diagnosed by comparing the predetermined data shifted by the shifting means to the predetermined data.

EMBODIMENT OF THE INVENTION Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a system control device 1 according to an embodiment of the present invention includes a diagnostic control circuit 11, a request reception flip tool tip (hereinafter referred to as tFF) 12, and a request code register 13. , a reception address register 14, a reception data register 15,
The decoder 16, the step counter 17, the selector 18, one shifter, the flip-flops (hereinafter referred to as memory rifnis 1 to FF) 20 to the memory rifnis 1, the rifniss 1 to address register 21, and the lie 1 to data register 22. , a read data register 23, a comparator 24, analogues 1 to 25, and memory diagnostic request FFs 1 to flip-flops (hereinafter referred to as memory diagnostic request FF) 26, which are connected to the memory 2. has been done.

= 5- When the diagnosis of the memory 2 is performed, rifnis 1 to 101 from the processing device side (not shown), a code 102 to the rifnis 1 without memory diagnosis to the rye 1, and an address 103 indicating the initial value of the address. and data 104 indicating the initial values of RIE 1 to data are input to the system control device 1.

In the system control device 1, the refnis 1 to 101 are stored in the request reception FF 12, the refnis 1 code 102 is stored in the request code register 13, the address 103 is stored in the ``ready'' address register 14, and the data 104 is stored in the reception data register 15. .

When the request 101 is stored in the request reception FF 1.2, the decoder 16 sends the request 101 to the reception FF 1.
Request code register 13 by the output signal from 2
Decodes the contents of the memory rifnis 1 to code 102 stored in the memory rifnis 1 to 102 to indicate that it is a write request.
105 is output to the memory rifice l-F'F 20, and the memory diagnostic rifice l-FF26 is set.

When memory diagnosis Rifnis1~FF26 or Sen1- is done,
A memory diagnosis request 106 is outputted from the memory diagnosis filters 1 to FF 26 to the selector 18, one shifter, and the AND gate 25, respectively. This memory diagnosis request 106 is outputted from the memory diagnosis request PF 26 after the initial values of addresses are set in the address register 21 and the initial values of data are set in the write data register 22.

When the selector 18 receives the memory diagnosis refresh h106 from the memory diagnosis request FF 26, it selects the output signal from the step counter 17 and outputs it to the refresh change 1 to the address register 21. Further, when the memory diagnosis request 106 from the memory diagnosis request FF 26 is input, the shifter 19 shifts the data input from the write data register 22 and transfers the data to the write data register 22.
Output to.

Request 101 is stored in the request reception FF 12, and the output signal of the request reception FF 12 becomes "1".
When the output signals from the memory diagnostic refnis 1 to FF 26 become '1' due to the decoded signal from the decoder 16, the output signal from the AND gate 25 becomes '1'.
During the memory address range defined by the diagnostic control circuit 11 when performing memory diagnosis, that is, for a certain period of time, the output signal from the request reception FF 12 becomes '1'°,
This enables the decoder 16 to output.

From the selector 18, the address obtained by incrementing the memory address 108 from the request address register 21 by the increment counter 17 is output to the rifnis 1-address register 21, and the diagnostic control circuit 11 receives the request (-I).
Riff varnish 1~until outputting 0°' to F F 12
The value of memory address 108 from address register 21 to memory 2 is sequentially incremented.

Also, from the shifter 19, the value obtained by shifting the data from the write data register 22 to the shift 1 is transferred to the write data register 2.
2, the contents of the write 1 data 109 from the write data register 22 to the memory 2 are sequentially shifted until the diagnostic control circuit 11 outputs 0'' to the request reception FF 12.

Since the memory request FF20 indicates a write request and outputs a memory request 107 indicating a write request to the memory 2, different write data is written to a different memory address in each cycle in the memory 2. becomes.

When writing of the write data to the memory 2 is completed, the processing device sends a request 101 indicating a read request.
and request code 102 indicating read memory diagnosis.
Then, an address 103 indicating the same address as the initial value of the address set at the time of writing to the memory 2, and data 104 indicating the initial value of the write data, that is, the comparison data are output to the system control device 1.

In the system control device 1, the request 101 is stored in the request reception FF 12, the request code 102 is stored in the request code register 13, the address 103 is stored in the reception address register 14, and the data 104 is stored in the reception data register 1.
5 respectively.

When the riff varnish 1-101 is stored in the rif varnish 1 to the reception FF 12, the decoder 16 decodes the contents of the request code 102 stored in the request code register 13 to the rif varnish 1 based on the output from the reception FF 12, and determines that it is a read request. A memory request 105 indicating the above is output to the memory request FF 20, and a memory diagnosis request FF 26 is set.

After this, in the same manner as the write operation to the memory 2 described above, the memory address 108 from the request address register 21 to the memory 2 is sequentially incremented, and the write data 109 output from the write 1 to data registers 22 is sequentially shifted. be done.

During this time, since a memory request 107 indicating a read request is input to the memory 2, the read data 110 is output to the system control device 1 from the address indicated by the memory address 108 from the request address register 21.

Read data 110 from memory 2 is stored in read data register 23 and compared with write data 109 from write data register 22 in comparator 24 . From the write data register 22, the same data as the data written to the memory 2 during the previous write is l1ll'f next shift 1.
. . . . Therefore, it is possible to check whether the data written to the memory 2 by the diagnostic request of the write request has been written.

FIG. 2 is a diagram showing the contents written in the memory 2 by the system control device 1 of FIG. In the figure, when the shifter 19 is a 1-bit shifter that performs a shift operation one bit at a time, the initial value of the line data is "' oooo
. . . shows the contents of the memory 2 when 01'° is sequentially shifted by 1 and written to the memory 2.

The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

When diagnosing memory 2, a request 101 from the processing device side, a request 101 indicating no write memory diagnosis, a code 102, and an initial value of the address ``address AO'' are sent.
When the address 103 indicating ``J'' and the data 104 indicating the initial value of data ``''oooo...01'' are input to the system control device 1, the request 101 becomes the request code FF1. -2,
Riffnis1~Code1()2 is stored in Riffnis1~Code register 13, and address 103 is stored in reception address register 1.
4, the data 104 is stored in the lie 1 data register 15, respectively.

Riff varnish 1 to 1 ((JFI” 12 to ref varnish 1 to 10)
1 is stored, the decoder 16 decodes the contents of the request code 102 stored in the code register 13 from the request code 1 to the code register 13 based on the output from the request code 1 to the reception FF 12, and writes the memory request code 102 indicating that it is a write request.
~105 is output to the memory rifice l-F F 20, and the memory diagnostic rift varnish l-F F 26 is output to the cell 1~.

At this time, the initial address value "address AO," is stored in the refnis 1 to address register 21, and the initial data value "oooo..." is stored in the write data register 22.
-01pa is stored.

As a result, memory 2 is set to address AO by memory requests 1 to 107 from memory request FF20.
oooo...01''' is written.

Subsequently, the address A1 incremented by the step counter 17 is output to the memory 2 as the memory address 108, and the shifter 19 shifts the data "ooo".

......10'° is output to the memory 2 as the write data 109, so in the memory 2, "'0000...10' is written to the address A1 by the memory request 107 from the memory refinis l-FF20. ” is written.

Similarly, the step counter 17 sequentially stores (J
The data sequentially shifted from 1 to 1 by the shifter 19 to the advanced addresses A2 to An are 0000...0100.
"~"1000...00" are written.

'1000...' to memory 2 address All
When the write operation to the memory 2 is completed by writing 00'', the processing device does not issue a read request and sends rifnis l-101 and riffnis indicating read memory diagnosis).
Code 102 and address 1 indicating address AO, which is the same as the initial value of the address set when writing to memory 2.
03, and the initial value of the write data, that is, the comparison data, is “0”.
000...01''' and data 104 are output to the system control device 1.

In the system control device 1, the request 101 is the request 101
to the reception FF 12, to the rifice 1 code 102 or the rifice 1 to coat register 13, the address 103 or the reception address register 14, and the data 104 to the reception data register 15, respectively.

Riff varnish 1-1 (-IFF 1.2 to Riff varnish 1-10
When 1 is stored, the decoder 16 uses the request reception FF
Riffnis 1-code register 13 by the output from 12
Memory refnis 1 to 1 decodes the contents of the request code 102 stored in the memory request code 102 and indicates that it is a read request.
05 is output to the memory rifice 1 to FF20, and the memory diagnosis rifice 1 to FF26 are output to the memory revise 1 to FF26.

After this, in the same manner as the two series of write operations to the memory 2, the memory address 108 from the request address register 21 to the memory 2 is sequentially incremented, and the write 1 to data 109 output from the write data register 22 are Sequential shift I- is performed.

-1, 4-- During this time, a memory request 107 indicating a read request is input to the memory 2, and data is sent from addresses AO to An indicated by memory address iQ8 from the refnis 1 to address register 21. ooooo...
. . 01'" to "1ooo . . . 00'' are sequentially read out and output as read data 110 to the system control device 1.

Read data 110 from memory 2 is stored in read data register 23 and compared with data 109 from lie I-data register 22 to lie 1 in comparator 24 . That is, first, data "'oo" read from address AO of memory 2 and stored in read data register 23
oo...01'' and data register 2 to lie 1
The comparator 24 compares the initial value "oooo...01" stored in the memory 2.

Thereafter, the data "'oo" read from addresses A1 to An of the memory 2 and stored in the read data register 23
oo...10''~'MOOO...00
''', and the data "oooo...1" which was sequentially shifted by shifter 1 and stored in the write data register 22.
The comparator 24 sequentially compares the 0 parameters with "'1000...00'" to determine whether the data written to the memory 2 by the write request diagnosis request 1~ was written correctly. You can check.

In this way, the memory address 108 sequentially incremented by the step counter 17 selected by the selector 18 is transferred to the memory 2 held in the memory diagnosis rifice 1-F F26.ノ(Give me,
By writing the data sequentially shifted by the shifter 1 according to the memory diagnosis request held in the memory diagnosis request FF 26 to the memory 2, and then supplying the memory address 108 sequentially incremented by the step counter 17 to the memory 2. Data read from memory 2 and thick 1
Memory 2
By performing this diagnosis, different data ``'oooo'' can be sent to different addresses AO-An of memory 2 with a single write memory diagnosis request from the processing device side.
...01'' to "1000...00" can be written, so mutual interference errors can be easily discovered.

In addition, even when trying to write different data patterns to memory 2 and check them, the processing device side can send requests for write 1-memory diagnosis and read memory without outputting requests for the different data patterns. Since it is only necessary to output the request for diagnosis, the burden on the processing device that outputs the request for diagnosis 1- can be reduced.

In one embodiment of the present invention, a case will be described in which a shifter 19 that performs a shift operation one bit at a time is used, but this is not limited to this as long as it is a circuit that can output various data.

As explained above, according to the present invention, a predetermined address from the diagnostic device that is sequentially incremented according to the questions 1 to 1 from the diagnostic device held in the request holding means is supplied to the memory, and the request After writing predetermined data from the diagnostic device to the memory, which is sequentially shifted by, data is read from the memory by a predetermined address, which is sequentially incremented;
By comparing the sequentially shifted predetermined data and diagnosing the memory, mutual interference errors can be easily discovered, and the burden on the processing device that outputs Riffnis 1~ can be reduced. There is an effect that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the contents of the memory written during memory diagnosis according to the embodiment of the present invention. Explanation of symbols of main parts 1...System control device 2...Memory 11...Diagnostic control circuit 12...Request reception flip-flop 17... ...Step counter 18...Selector 19...Shifter 20...Memory refresh 1~Flip-flop = 18-21...Request address register 22...
. . . Read data register 24 . . . Comparator 26 . . . Memory diagnostic refinish 1 to flip-flop

Claims (1)

[Claims] (1) A request holding means for holding a request from a diagnostic device to a memory, and an address supplying device that sequentially increments a predetermined address from the diagnostic device and supplies it to the memory according to the request held in the request holding device. and a shift means for sequentially shifting predetermined data from the diagnostic device according to the request held in the request holding means, and supplying the address in response to a write request from the diagnostic device held in the request holding means. After writing the predetermined data shifted by the shifting means to the address supplied from the means,
Comparing data read from the memory at an address supplied from the address supply means in response to a read request from the diagnostic device held in the request holding means and the predetermined data shifted by the shift means. A memory diagnostic method characterized in that the memory is diagnosed.