JP2010054402A - Circuit testing device, circuit test program, and circuit test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a failure detection rate of a design object circuit effectively in a power saving way. <P>SOLUTION: When acquiring design data of a design object circuit having a function corresponding to a customer need, this circuit testing device 100 generates a circuit testing mechanism 110 enabling failure detection corresponding to whether an object circuit 102 designated as a test object is an OR circuit or an AND circuit, in the design object circuit. The circuit testing device 100 also has a function for executing an operation test of the object circuit 102 by the generated circuit testing mechanism 110. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit test apparatus, a circuit test program, and a circuit test method for detecting a failure of a circuit to be designed in a circuit design process.

  Conventionally, many steps are required until an ASIC (Application Specific Integrated Circuit) is designed, mounted on an actual machine, and shipped as a product. FIG. 7 is a flowchart showing a procedure from conventional ASIC design to shipment. Each process will be described with reference to FIG. 7. First, the designer receives customer needs (step S701), and performs request analysis from the received customer needs (step S702). This is an operation to create a required specification that defines what kind of service the system provides and regulates the constraint conditions related to system operation.

  Furthermore, after clarifying the customer's required specification by the processing in step S702, system design is performed in order to formulate a specification as a system necessary for realizing the required specification (step S703). Then, the operation processing of the circuit is determined based on the operation specification, and the architecture and function are designed using the circuit description language (step S704). Next, in step S704, logic design is performed in order to convert the logic expressed in the circuit description language into a logic circuit (step 705), thereby mapping to a library cell of a desired technology.

  Thereafter, as a test design process, a circuit having a test mechanism capable of detecting a transistor failure in the manufacturing stage is designed (step S706), and inserted into the logic circuit designed in step S705. Thereafter, based on the test result of the circuit (circuit provided with the test mechanism) set by the processes up to step S706, layout design relating to placement and wiring is performed on the ASIC device (step S707). Then, the ASIC designed in 707 designed in step S707 is manufactured, and an evaluation test is further performed using an actual product (step S708). If it is determined that the product is non-defective as a result of the test, the product is first shipped as a product (step S709).

  In addition, as a technique for determining the quality of the ASIC in the ASIC shipping test in step S708, a circuit test technique using a test pattern is generally used. This is because a specific pattern in the ASIC input signals “0” and “1” is input, and a value called an expected value is compared with a “0” and “1” pattern from the output terminal. If the values match, it is judged as a non-defective product.

  When such a test pattern is used, a technique called a scan test using a scan chain is often used. FIG. 8 is an explanatory diagram showing the procedure of the scan test using the scan chain. In the case of a scan test using a scan chain, a test using the test pattern as described above is performed in a state where the connection of FFs created for an ASIC test is connected like a shift register as in the design target circuit 800. In normal operation, as indicated by the solid line arrow, the path is connected from the D terminal of the FF to the Q terminal. A sequential circuit exists on this path. On the other hand, connections (broken arrows) prepared as scan chains are connected from the signal input terminal (SIN) to the signal output terminal (SOUT) of each FF as a shift register. Which of these normal operation connection and scan chain connection is valid can be controlled by a test mode switching signal.

  That is, at the time of test execution, '0' and '1' patterns are input from the SIN terminal, and are output to the SOUT terminal through the SIN / SOUT terminals of each FF as indicated by the broken line arrows in FIG. In addition, a technique is also used in which a signal taken in from the D terminal of the FF is output to the SOUT terminal of the FF and output to the SOUT terminal by a shift operation (for example, see Patent Document 1 below).

JP 2004-184316 A

  In the evaluation test at the time of shipment of the ASIC as described above, a rate at which a fault inside the circuit can be detected is called a fault detection rate. This can be expressed as “B / A”%, where “A” is the total number of terminals of the logic cell in the circuit and “B” is the number of terminals from which a failure can be detected. In order to be able to correctly judge pass / fail in the ASIC test, a circuit test is required to make the failure detection rate close to 100%, that is, to detect failure from all terminals as much as possible.

  However, among the conventional circuit tests, the scan test cannot comprehensively detect failures for all the circuits in the design target circuit. In addition to the scan test, there is also provided a method for detecting a failure of each circuit by automatically generating various test patterns by ATPG (Automatic Test Pattern Generator). The test pattern generated by ATPG is also provided. Then, for circuits that cannot be activated, additional patterns must be created and activated individually. As a result, there is a problem that both the verification time and the test time are enormous processing, and the processing efficiency and cost are heavy.

  The present invention provides a circuit test apparatus, a circuit test program, and a circuit test method capable of labor-saving and effectively improving the failure detection rate of a circuit to be designed in order to eliminate the above-described problems caused by the prior art. The purpose is to do.

  In order to solve the above-described problems and achieve the object, the circuit test apparatus, the circuit test program, and the circuit test method include a process for accepting designation of a test target circuit from among design target circuits, and a stage preceding the accepted test target circuit. A process for identifying the logic circuit connected to the mask, a mask circuit for masking the output from the logic circuit between the identified logic circuit and the circuit under test, and a control signal for controlling the mask process of the mask circuit And a process for generating a circuit test mechanism including an input terminal for a test signal to be input to the test target circuit.

  According to the circuit test apparatus, the circuit test program, and the circuit test method, by controlling the mask processing of the mask circuit, the output from the preceding logic circuit is shielded from the test target circuit, and the test target circuit is affected. You can avoid giving. Further, by inputting a test signal in a state where the output is shielded from the preceding logic circuit, it is possible to verify only the operation of the circuit under test.

  According to the circuit test apparatus, the circuit test program, and the circuit test method, there is an effect that the failure detection rate for the circuit to be designed can be improved labor-saving and effectively.

  Exemplary embodiments of a circuit test apparatus, a circuit test program, and a circuit test method will be described below in detail with reference to the accompanying drawings. In this circuit test apparatus, circuit test program, and circuit test method, a circuit test mechanism including a mask circuit that shields an output from a logic circuit preceding the circuit to be tested is generated and inserted into the circuit to be tested. Efficient circuit test can be easily realized.

(Outline of circuit test)
First, the outline of the circuit test according to the present embodiment will be described. FIG. 1 is an explanatory diagram showing an outline of a circuit test according to the present embodiment. In the circuit test apparatus 100, when design data of a design target circuit having a function according to customer needs (hereinafter referred to as “design target circuit data”) is generated, the design target circuit data is acquired and the design target circuit is acquired. Among them, the circuit test mechanism 110 for enabling the failure detection of the target circuit 102 designated as the test target is generated. That is, in the test design process of step S706 described with reference to FIG. 7, processing related to DFT (Design For Testability) is performed. The circuit test apparatus 100 also has a function of executing an operation test of the target circuit 102 by the generated circuit test mechanism 110.

  The circuit test mechanism 110 includes a mask circuit 111, a control signal input terminal 112, and a test signal input terminal 113. The generated circuit test mechanism 110 is inserted between the target circuit 102 and the logic circuit 101 preceding the target circuit 102. The mask circuit 111 of the circuit test mechanism 110 masks the output from the logic circuit 101 in accordance with the control signal input from the control signal input terminal 112. For example, if the control signal is ON, the mask circuit 111 masks the output from the logic circuit 101. Accordingly, the output from the logic circuit 101 is not input to the target circuit 102.

  If the control signal is OFF, the mask circuit 111 does not mask the output from the logic circuit 101. Therefore, the output from the logic circuit 101 passes through the mask circuit 111 and is input to the target circuit 102 as it is. That is, when it is desired to execute a normal circuit operation instead of a circuit test, the control signal may be turned off.

  A test signal for verifying the operation of the target circuit 102 is input from the test signal input terminal 113 during the circuit test. That is, at the time of the circuit test, since the control signal is in the above-described state, the output from the logic circuit 101 is not input to the target circuit 102, and only the test signal input from the test signal input terminal 113 is input. Is entered. Therefore, it is possible to detect a failure of the target circuit 101 by holding the output of the target circuit 102 in a state where the control signal is ON.

  Hereinafter, a specific configuration and operation for realizing the circuit test described with reference to FIG. 1 will be described.

(Hardware configuration of circuit test equipment)
First, the hardware configuration of the circuit test apparatus 100 will be described. FIG. 2A is a block diagram illustrating a hardware configuration of the circuit test apparatus 100. 2A, the circuit test apparatus 100 includes a CPU (Central Processing Unit) 201, a ROM (Read-Only Memory) 202, a RAM (Random Access Memory) 203, a magnetic disk drive 204, a magnetic disk 205, and the like. An optical disk drive 206, an optical disk 207, an I / F (Interface) 208, an input device 209, and an output device 210. Each component is connected by a bus 200.

  Here, the CPU 201 governs overall control of the circuit test apparatus 100. The ROM 202 stores programs such as a boot program and a test circuit design program. When the circuit test apparatus 100 performs not only the test design process but also processes related to other processes such as the logic design in step S705 and the layout design in step S707 as described in FIG. A program corresponding to the processing content is also stored. The RAM 203 is used as a work area for the CPU 201. The magnetic disk drive 204 controls reading / writing of data with respect to the magnetic disk 205 according to the control of the CPU 201. The magnetic disk 205 stores data written under the control of the magnetic disk drive 204.

  The optical disk drive 206 controls reading / writing of data with respect to the optical disk 207 according to the control of the CPU 201. The optical disk 207 stores data written under the control of the optical disk drive 206, or causes the computer to read data stored on the optical disk 207.

  An interface (hereinafter abbreviated as “I / F”) 208 is connected to a network 211 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and other networks are connected via this network 211. It is connected to a device (for example, a device that performs the logical design in step S705 described in FIG. 7 or the layout design in step A707). The I / F 208 controls an internal interface with the network 211 and controls input / output of data from an external device. For example, a modem or a LAN adapter can be adopted as the I / F 208.

  The input device 209 can receive an instruction from the designer to the circuit test apparatus 100. Examples of the configuration of the input device 209 include a keyboard and a mouse. If it is a keyboard, it has keys for inputting letters, numbers, various instructions, etc., and can input data. The keyboard is not limited to a general keyboard type, and may be a touch panel type input pad or a numeric keypad. In the case of a mouse, the cursor can be moved, a range can be selected, or a window can be moved and its size can be changed. In addition, a trackball, a joystick, or the like may be used as long as it has the same function as a pointing device.

  The output device 210 can output the processing result by the circuit test apparatus 100 to the verifier. Examples of the configuration of the output device include a display and a printer. If it is a display, it can display data such as a cursor, an icon or a tool box, a document, an image, and function information. Further, if it is a printer, it is possible to print data relating to the generated test netlist.

(Functional configuration of circuit test equipment)
Next, a functional configuration of the circuit test apparatus 100 will be described. FIG. 2-2 is a block diagram illustrating a functional configuration of the circuit test apparatus. The circuit test apparatus 100 includes a receiving unit 221, a specifying unit 222, a generating unit 223, and a detecting unit 224. Specifically, the functions (accepting unit 221 to detecting unit 224) serving as the control unit are, for example, programs stored in a storage area such as the ROM 202, the RAM 203, the magnetic disk 205, and the optical disc 207 shown in FIG. Is executed by the CPU 201 or by the I / F 208.

  When the design target circuit data is input, the reception unit 221 receives designation of a circuit to be tested (for example, the target circuit 102 in FIG. 1) from the design target circuits. Designation of a circuit to be tested is realized, for example, by receiving input from the input device 209 from a verifier or a host system that performs a circuit test of the circuit to be designed. In the present embodiment, all circuits included in the design target circuit can be designated as verification targets. Therefore, in order to realize the failure detection of all the circuits included in the design target circuit, it may be sequentially set to the test target circuit, or in combination with the conventional method, the circuit that cannot detect the failure by the conventional method ( For example, only a circuit that could not be activated by ATPG may be designated as a test target circuit. The received circuit designation instruction is temporarily stored in a storage area such as the RAM 203, the magnetic disk 205, or the optical disk 207.

  The specifying unit 222 specifies a logic circuit (for example, the logic circuit 101 in FIG. 1) connected to the previous stage of the test target circuit received by the receiving unit 221. In order to identify the logic circuit connected to the previous stage of the test target circuit, for example, the connection of the test target circuit may be fed back in the design target circuit data input to the receiving unit 221. Information on the logic circuit specified by the specifying unit 222 is stored in a storage area such as the RAM 203, the magnetic disk 205, and the optical disk 207.

  The generation unit 223 masks output from the logic circuit between the logic circuit specified by the specifying unit 222 and the test target circuit (for example, the mask circuit 111 in FIG. 1), and performs mask processing of the mask circuit. A circuit test mechanism including an input terminal for a control signal to be controlled (for example, control signal input terminal 112 in FIG. 1) and an input terminal for a test signal to be input to the test target circuit (for example, test signal input terminal 113 in FIG. 1) Is generated.

  In addition to the configuration described above, the generation unit 223 further includes a register that holds the output from the circuit under test for each clock cycle, and a comparator that compares the values of successive clock cycles held in the register. A circuit test mechanism may be generated. In addition, the generation unit 223 outputs design data of a circuit in which the generated circuit test mechanism is inserted into the design target circuit, that is, a design target circuit that has become a test facilitating circuit. This design data is used for the processing in step S707 described with reference to FIG.

  Further, as described above, the generation unit 223 can also perform an operation test of the target circuit 102. When such processing is performed, the generation unit 223 further generates a circuit test mechanism including a register that holds an output from the test target circuit and a comparator that compares the values held in the register. By outputting the comparison result of the comparator to the detection unit 224, which will be described later, it is possible to automatically realize failure detection for the operation of the circuit under test.

  When the test signal input from the test input terminal is input after the input to the circuit under test is masked by the control signal, the detection unit 224 matches the values of successive clock cycles by the comparator of the circuit test mechanism. The failure of the circuit under test is detected according to whether or not to do so. For example, after holding a predetermined value in the register and inputting the same value as the predetermined value as a test signal to the test target circuit, if the operation of the test target circuit is normal, the same value as the predetermined value is stored in the register The value of is held. Therefore, if the operation of the circuit under test is normal, the comparator determines that the values of successive clock cycles match. That is, if the values of successive clock cycles do not match in the comparator, the detection unit 224 can detect a failure and output failure data because the operation of the circuit under test is not normal.

  As described above, the function of the circuit test apparatus 100 according to the present embodiment includes a function for generating a circuit test mechanism for performing a circuit test on a circuit to be tested, and a failure using the generated circuit test mechanism. It is roughly divided into two functions: a detection function. Therefore, in the following, specific procedures will be described separately for each function of circuit test mechanism generation and circuit test.

(Circuit for generating circuit test mechanism)
First, a procedure for generating a circuit test mechanism in the circuit test apparatus 100 will be described. FIG. 3 is a flowchart showing a generation procedure of the circuit test mechanism. In the flowchart of FIG. 3, it is first determined whether or not circuit data to be designed has been acquired (step S301). Here, the process waits until the design target circuit data is acquired (step S301: No loop). When the design target circuit data is acquired (step S301: Yes), the test target circuit is specified from the design target circuit. It is determined whether or not (step S302).

  In step S302, whether or not the test target circuit is specified is determined in the receiving unit 221 depending on whether or not an instruction from the verifier is received. In this case as well, the process waits until the test target circuit is specified (step S302: No loop). When the test target circuit is specified (step S302: Yes), the specified test target circuit and the preceding logic circuit are connected. Specify (step S303). That is, in this step S303, the logic circuit from which the test target circuit is influenced is specified. Then, a circuit test mechanism is generated between the test target circuit specified in step S303 and the preceding logic circuit (step S304), and the series of circuit test generation processes is terminated.

(Circuit test procedure)
Next, a circuit test procedure in the circuit test apparatus 100 will be described. 4A to 4C are flowcharts illustrating the circuit test procedure. In the flowchart of FIG. 4A, first, the test signal is set to the OFF state (step S411). Then, the process proceeds to a process of masking the output from the logic circuit 101 in the previous stage of the target circuit 102 to be tested. Specifically, a control signal for performing a mask instruction is input from the mask control signal input terminal 112 to the mask circuit 111 (step S412).

  As a result of the processing in step S412, '0' is always input to the target circuit 102 from the preceding logic circuit 101. That is, the test target circuit itself is in the “0” output state. Then, the target circuit 102 is tested. At this time, the operation in the circuit test mechanism is different depending on whether the target circuit 102 is an OR circuit or an AND circuit. Therefore, the target circuit 102 is an OR circuit or an AND circuit. It is determined whether or not there is (step S413).

  First, processing when the target circuit 102 is an AND circuit will be described. If it is determined in step S413 that the target circuit 102 is an AND circuit (step S413: AND), then an all 0 instruction is input from the external terminal for setting in the flowchart of FIG. 4-2 (step S421). The external terminal for setting is a dedicated input terminal for setting a register value generated as a circuit test mechanism. Since ‘0’ or ‘1’ is input from the outside, the register is set to ‘0’ or ‘1’. Then, “0” is held in the register by 0 input in step S421 (all 0 set).

  Therefore, it is next determined whether or not all the values continuously stored in the register by the comparator are “0”, that is, all 0 (step S422). If it is determined by the all 0 check in step S422 that it is not all 0 (step S422: No), the detection unit 224 determines that the target circuit 102 is a defective product causing one stuck-at fault (step S426). Then, a series of processing is completed.

  On the other hand, if it is determined in step S422 that all 0s are set (step S422: Yes), an all 1 instruction is further input from the setting external terminal (step S423). By this processing of step S423, "1" is held in the register this time (all 1 set). Then, it is determined whether or not the values continuously held in the registers by the comparator are all “1”, that is, all 1 (step S424).

  When it is determined by the all 1 check in step S424 that it is not all 1 (step S424: No), the detection unit 224 determines that the target circuit 102 is a defective product causing a 0 stuck-at fault (step S426). A series of processing ends. On the other hand, if it is determined in step S424 that all 1s are satisfied (step S424: Yes), the target circuit 102 is determined to be a non-defective product that operates normally (step S425), and the series of processes is terminated.

  Next, processing when the target circuit 102 is an OR circuit will be described. If it is determined in step S413 that the target circuit 102 is an OR circuit (step S413: OR), next, an all-one instruction is input from the setting external terminal in the flowchart of FIG. 4-3 (step S431). By the input in step S431, “1” is held in the register in the detector 224 (all 1 set).

  Next, it is determined whether or not the values continuously held in the register by the comparator are all “1”, that is, all 1 (step S432). When it is determined by the all 1 check in step S432 that it is not all 1 (step S432: No), the detection unit 224 determines that the target circuit 102 is a defective product causing a 0 stuck-at fault (step S436). Then, a series of processing is completed.

  On the other hand, if it is determined in step S432 that all 1s are set (step S432: Yes), an all 0 instruction is input from the setting external terminal (step S433). By this process of step S433, “0” is held in the register this time (all 0 set). Then, it is determined whether or not the values continuously held in the registers by the comparator are all “0”, that is, all 0 (step S434).

  If it is determined by the all 0 check in step S434 that it is not all 0 (step S434: No), the detection unit 224 determines that the target circuit 102 is a defective product causing one stuck-at fault (step S436). A series of processing ends. On the other hand, if it is determined in step S434 that all 0s are present (step S434: Yes), the target circuit 102 is determined to be a non-defective product that operates normally (step S435), and the series of processing ends.

  As described above, the circuit test apparatus 100 generates a circuit test mechanism with an optimal and easy configuration according to the target circuit 102 designated as the test target, and uses the generated circuit test mechanism to efficiently In addition, failure detection of the target circuit 102 can be realized. As described with reference to FIGS. 4A to 4C, even when the same circuit test is performed on different target circuits 102, the target circuit 102 is an OR circuit or an AND circuit. Therefore, the circuit testing mechanism is required to have a configuration corresponding to the type of circuit. Therefore, specific configurations and operation contents will be described below for a case where the target circuit 102 is an OR circuit and an AND circuit, respectively, as circuit test configurations.

(Circuit test configuration 1: OR circuit)
First, as a circuit test configuration 1, a test configuration when an OR circuit is a test target circuit will be described. FIG. 5 is a circuit diagram showing a configuration example of the circuit test mechanism 1. In the circuit 500, OR1 is the target circuit. Therefore, AND1 is inserted as a mask circuit for masking the output from the user circuit 510, which is the logic circuit preceding the OR1. Further, the output of the target circuit OR1 is output to the detector 520 of the circuit test mechanism in addition to a normal connection circuit (GCB: Gated Clock Buffer).

  When performing a circuit test, first, the test signal is turned off. With this setting, the target circuit OR1 enters a state of passing through the output from the mask circuit AND1. Next, in order to mask the output of the user circuit 510, ‘0’ is input from the mask control signal input terminal. By this “0” input, the output of the mask circuit AND 1 becomes “0”, and the output of the target circuit OR 1 also becomes “0”.

  Then, “1” is input from the external terminal for setting. Then, a 1-cycle clock is input from the Clock terminal, and “1” is held in the register 521 inside the detector 520. By this operation, “1” is set in all the registers 521 in the detector 520. Then, the comparator 501 compares the values continuously held (for two cycle clocks) in the register 521.

  Here, when the value input to the register 521 is all 1, the comparator compares ‘1’ with ‘1’ and outputs a value (for example, ‘0’) indicating that they match. On the other hand, when the input values do not match, the comparator 501 outputs a value (for example, “1”) indicating that they do not match. When a value indicating that they do not match is output, it is detected that the register 521 of the detector 520 has a 0 stuck-at fault, and the circuit test is terminated. Only when no failure is detected, the circuit test of the target circuit OR1 is started.

  First, “0” is input from the external terminal for setting. By this “0” input, “0” is again input to the register 521. Here, when one cycle clock is input from the Clock terminal, “0” is held in the register 521. Then, the comparator 501 compares the values continuously held (for two cycle clocks) in the register 521. When the input value is all 0, the output of the comparator 501 is a value “0” indicating that the compared values match, and is judged as a non-defective product. On the other hand, when the input values do not match, the comparator 501 outputs a value “1” indicating that they do not match. At this time, it is determined that one stuck-at fault has occurred in the target circuit OR1, and the circuit test for the target circuit OR1 ends.

(Circuit test configuration 2: AND circuit)
Next, as circuit test configuration 2, a test configuration in the case where an AND circuit is a test target circuit will be described. FIG. 6 is a circuit diagram showing a configuration example of the circuit test mechanism 2. In the circuit 600, AND2 is the target circuit. Therefore, OR3 is inserted as a mask circuit for masking the output from the user circuit 610 which is a logic circuit preceding the AND2. The test signal is input to the target circuit AND2 in a state inverted by NOT1. The output of the target circuit AND2 is output to the detector 620 of the circuit test mechanism in addition to a normal connection circuit (FF: Flip Flop).

  When performing a circuit test, first, the test signal is turned off. With this setting, the target circuit AND2 is in a state of passing through the output from the mask circuit OR3. Next, in order to mask the output of the user circuit 610, ‘1’ is input from the mask control signal input terminal. By this “1” input, the output of the mask circuit OR3 becomes “1”, and the output of the target circuit AND2 also becomes “1”.

  Then, “0” is input from the external terminal for setting. Then, a one-cycle clock is input from the Clock terminal, and “1” is held in the register 621 inside the detector 620. By this operation, “0” is set in all the registers 621 in the detector 620. Then, the comparator 601 compares the values continuously stored in the register 621 (for two cycle clocks).

  Here, when the value input to the register 621 is all 0, the comparator compares ‘0’ with ‘0’ and outputs a value (for example, ‘0’) indicating that they match. On the other hand, if the input values do not match, the comparator 601 outputs a value (for example, “1”) indicating that they do not match. If a value indicating that they do not match is output, it is detected that the register 621 of the detector 620 is one stuck-at fault, and the circuit test is terminated. Only when no failure is detected, the circuit shifts to the circuit test of the target circuit AND2.

  First, “1” is input from the external terminal for setting. By this “1” input, “1” is again input to the register 621. Here, when one cycle clock is input from the Clock terminal, “1” is held in the register 621. Then, the comparator 601 compares the values continuously stored in the register 621 (for two cycle clocks). When the input value is all 1, the output of the comparator 601 is a value “0” indicating that the compared values match, and is judged as a non-defective product. On the other hand, if the input values do not match, the comparator 601 outputs a value “1” indicating that they do not match. At this time, it is determined that a 0 stuck-at fault has occurred in the target circuit AND2, and the circuit test for the target circuit AND2 ends.

  As described above, by performing the procedure described with reference to FIGS. 5 and 6, it becomes possible to detect a failure in the circuit under test in which a fixed value has been input during the test period. The rate can be improved.

  As described above, according to the present embodiment, it is possible to detect a failure even at a location where a circuit test for improving the failure detection rate is impossible. Thereby, the failure detection rate can be improved. In addition, a circuit that cannot be activated by ATPG can be activated. Therefore, the test time can be greatly shortened as compared with the case where a circuit test is performed by generating an additional pattern as in the prior art. Therefore, the burden can be greatly reduced in terms of the amount of processing and cost of the verifier.

  Note that the circuit test method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, this program may be a medium that can be distributed via a network such as the Internet.

  In addition, the circuit test apparatus 100 described in the present embodiment can also be realized by a PLD (Programmable Logic Device) such as a standard cell, a structured ASIC, or an FPGA. Specifically, for example, the function of the circuit test apparatus 100 (receiving unit 221 to detecting unit 224) is defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD to perform circuit test. The device 100 can be manufactured.

It is explanatory drawing which shows the outline | summary of the circuit test concerning this Embodiment. It is a block diagram which shows the hardware constitutions of a circuit test apparatus. It is a block diagram which shows the functional structure of a circuit test apparatus. It is a flowchart which shows the production | generation procedure of a circuit test mechanism. It is a flowchart (the 1) which shows the procedure of a circuit test. It is a flowchart (the 2) which shows the procedure of a circuit test. It is a flowchart (the 3) which shows the procedure of a circuit test. It is a circuit diagram which shows the example of 1 structure of a circuit test mechanism. It is a circuit diagram which shows the structural example of the circuit test mechanism 2nd. It is a flowchart which shows the procedure from the conventional ASIC design to shipment. It is explanatory drawing which shows the procedure of the scan test by a scan chain.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Circuit test apparatus 101 Logic circuit 102 Target circuit 110 Circuit test mechanism 111 Mask circuit 112 Control signal input terminal 113 Test signal input terminal 221 Reception part 222 Identification part 223 Generation part 224 Detection part

Claims (7)

Receiving means for receiving a test target circuit from among the design target circuits;
A specifying means for specifying a logic circuit connected to the previous stage of the circuit to be tested received by the receiving means;
A mask circuit for masking an output from the logic circuit between the logic circuit specified by the specifying means and the test target circuit, an input terminal for a control signal for controlling mask processing of the mask circuit, and the test target Generating means for generating a circuit test mechanism including an input terminal of a test signal to be input to the circuit;
A circuit test apparatus comprising:   The generation unit further generates a circuit test mechanism including a register that holds an output from the test target circuit every clock cycle and a comparator that compares values of successive clock cycles held in the register. The circuit test apparatus according to claim 1.   In the circuit test mechanism, when a test signal is input from the input terminal of the test signal after the input to the circuit under test is masked by the control signal, the values of successive clock cycles match by the comparator. The circuit test apparatus according to claim 2, further comprising a detection unit configured to detect a failure of the test target circuit according to whether or not to perform the test. When the circuit under test is an OR circuit,
The circuit test apparatus according to claim 1, wherein the mask circuit is configured by an AND circuit that receives an output from the logic circuit and an input of the control signal. When the circuit under test is an AND circuit,
The circuit test according to claim 1, wherein the mask circuit includes an OR circuit that receives an output from the logic circuit and an inverted value of an input of the control signal. apparatus. Computer
Accepting means for receiving the test target circuit from the design target circuit,
A specifying means for specifying a logic circuit connected to a preceding stage of the test target circuit received by the receiving means;
A mask circuit for masking an output from the logic circuit between the logic circuit specified by the specifying means and the test target circuit, an input terminal for a control signal for controlling mask processing of the mask circuit, and the test target Generating means for generating a circuit test mechanism including an input terminal of a test signal input to the circuit;
Circuit test program characterized by functioning as Computer
A reception process for receiving a test target circuit from among the design target circuits;
A specifying step for specifying a logic circuit connected to the previous stage of the circuit under test received by the receiving step;
A mask circuit for masking an output from the logic circuit between the logic circuit specified by the specifying step and the test object circuit, an input terminal of a control signal for controlling mask processing of the mask circuit, and the test object A generation step of generating a circuit test mechanism including an input terminal of a test signal input to the circuit;
The circuit test method characterized by performing.

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