JPH0148568B2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Technical Field of the Invention The present invention provides an abnormality detection and display control method, particularly in a large/medium-sized data processing system equipped with a service processor, which enables flexible abnormal state detection and display. The present invention relates to an abnormality detection and display control method.

(B) Conventional technology and problems Figure 1 shows an example of the conventional method. Conventionally, abnormal states have been displayed by transmitting signals from latches 3-1 to 3-6 provided in the central processing unit 1, main memory control unit 2, etc. that indicate abnormal states, as shown in FIG. 1, for example. Lead to the console 4, various abnormal status display lamps 5-1 to 5- on the panel
This was done by lighting up the 2nd class. Therefore, there is a problem in that the abnormal conditions are uniquely and fixedly determined, are not flexible, and it is difficult to add or change the abnormal conditions.

In some systems, depending on operating conditions, it is often necessary to make a characteristic state immediately recognizable as an abnormal state, while in other systems it is necessary to operate the same state as a normal state. Therefore, it is desirable that the system be able to arbitrarily define abnormal conditions.

(C) Purpose and Structure of the Invention The present invention aims to solve the above-mentioned problems, and uses a scan-out circuit that has been conventionally used for maintenance and diagnosis, based on abnormal conditions arbitrarily set in advance. It is an object of the present invention to provide an abnormality detection display control method that detects an abnormal state and displays the detection result on, for example, a CRT display device. Therefore, the abnormality detection display control method of the present invention is
In a system equipped with a service processor that operates and controls the system and a scanout circuit that reads and collects the internal state of the hardware of each device, a condition setting section that presets the conditions that should be reported as an abnormal state of the system. and an address setting section that sets the scanout address assigned to the hardware corresponding to the condition set in the condition setting section in the scanout address register, and the scanout address set in the address setting section. The internal state detected by the internal state detection section reads out the internal state extracted by the address, and the state detected by the internal state detection section or the state forcibly set by the operation command is set in advance in the condition setting section. The present invention is characterized by comprising an abnormal state determining section that determines whether or not the specified conditions are met, and an abnormal state display section that displays the determination result of the abnormal state determining section. This will be explained below with reference to the drawings.

(D) Embodiment of the invention FIG. 2 shows the configuration of an embodiment of the invention, FIG. 3 is a diagram for explaining an example of abnormal conditions, and FIG. 4 explains the abnormal setting state storage section shown in FIG. 2. FIG. 5 shows a processing explanatory diagram of an embodiment of the present invention.

In the figure, 1 is the central processing unit (CPU), 10 is the service processor (SVP), 11 is the keyboard,
12 is a display device, 13 is a scanout circuit, 14-1 to 14-3 are latches, 5 is a decoder, 16 is a scanout address register, 17 is an ingate register, 18 is a command processing unit, and 19 is a condition. 20 is a setting section, 20 is an abnormal setting state storage section, 21 is a patrol section, 22
23 is an address setting section, 23 is an internal state detection section, and 24 is an address setting section.
25 represents an abnormal state determination section, and 25 represents an abnormal state display section.

The central processing unit 1 is a device that sequentially fetches and executes instructions and processes data. service·
The processor 10 has a processor independent of the central processing unit 1, and is a device that controls functions such as system operation and configuration control, and has a keyboard 11 and a display device 12. The scan-out circuit 13 is a circuit that reads latches 14-1 to 14-3, etc. that indicate various internal states of the central processing unit 1 and other devices, and is a circuit that has been conventionally prepared for system maintenance and diagnosis. be. The scan-out address register 16 is a register that specifies addresses of the latches 14-1 to 14-3, etc. assigned in advance. scanout address
The address set in the register 16 is decoded by the decoder 15 and sent to the latches 14-1 to 14-1.
Select 4-3. Selected latch 14-1~
The contents of 14-3 are taken into the ingate register 17. The service processor 10 sets an address in the scanout address register 16 and reads the contents of the ingate register 17, thereby being able to know the internal state of each device.

The command processing section 18 inputs various operation commands to the service processor 10 from the keyboard 11 and processes them. An example of an operation command related to the present invention is a force error (FER) command used for maintenance and diagnosis. For example, by keying in FER MEM, 100, 2, a 2-bit pseudo fault can be generated at address 100 in memory, making it possible to test whether error handling is performed correctly.

The condition setting unit 19 stores abnormal conditions regarding what kind of state is recognized as abnormal. For example, the abnormal conditions may be held in a table format, or may be held in a group of program instructions. FIG. 3 shows an example of abnormal conditions. For example, the third operation status register (OSPR3)
26 bits indicates that error checking is prohibited. The 29th bit of the same register is a so-called checkstop, which instructs the clock to stop in the event of an error. The 23rd bit is for disabling advance control of instructions. The 30th bit prohibits retry of the instruction. Also,
If any of the 0th to 15th bits of the second operation status register (OSPR2) is "1", a portion of the local memory has been disconnected, and the 22nd or 23rd bit is set to "1". If it is "1", it indicates that the address translation buffer is degraded. Each of these bits may be considered to correspond to the various latches 14-1 to 14-3 shown in FIG. For example, whether or not to perform local memory degradation depends on the system operation. Therefore, whether or not the degradation state of the local memory is considered to be an abnormal state depends on the operating conditions. That is, the condition setting unit 19 sets conditions for the above-mentioned internal state of the system to be abnormal. Abnormal conditions can be changed by converting the program or rewriting the table.

The abnormal setting state storage unit 20 stores the setting state when an abnormal state is forcibly created by the error force (FFR) command described above. For example, as shown in FIG. 4, it is provided in a system common area that is commonly accessible in the system. It stores the status such as whether a 1-bit or 2-bit error is set in the memory, whether an error is similarly set in the buffer memory, and whether it is in a maintenance/diagnosis state. In conventional hardware logic, it is difficult to display the setting state by such an operation command as an abnormal state, but in the case of the present invention, as can be seen from the following explanation, errors such as abnormal setting cancellation can be avoided. The status can be displayed as abnormal and a warning can be given to maintenance personnel.

The patrol unit 21 includes a service processor 1
For multi-task operation in 0, the address setting unit 22 is activated every several hundred milliseconds, for example. The address setting section 22 sequentially sets scan-out addresses corresponding to internal states to be detected in the scan-out address register 16 according to the contents of the condition setting section 19. The internal state detection unit 23 extracts the contents of the ingate register 17 specified by the scanout address register 16 and read out. The abnormal state determination unit 24
It is determined whether the information from the ingate register 17 matches the preset conditions of the condition setting section 19. Furthermore, it is also determined whether the abnormal setting state storage section 20 indicates an abnormal state. The abnormal state display section 25 is notified of the determination result of the abnormal state determination section 24. Abnormal state display section 25
This edits the abnormal state information, creates a display frame, and displays it on the CRT display device 12.

Next, with reference to FIG. 5, the flow of processing for detecting and displaying an abnormal state will be explained. When an opportunity to detect an abnormal state is given, first, in step 30, an item of the abnormal condition is extracted from the condition setting section. Next, by process 31,
A scanout address corresponding to that item is sent to the scanout circuit. And processing 3
In step 2, the contents of the ingate register are read, and in step 33, it is determined whether the state is abnormal. The determination results are stacked in the work area by process 34. In step 35, it is determined whether or not all items have been checked. If not, steps 30 to 34 are repeated until the check is completed.

Next, in process 36, the abnormal setting state storage unit is referred to, and it is determined whether the setting state caused by the abnormal operation is abnormal, and when it is abnormal, the result is stacked in process 37. Finally, in process 38, the stacked results are edited and displayed, and the presence or absence of an abnormal state is reported to the operator.

(E) Effects of the Invention As explained above, according to the present invention, abnormal conditions can be arbitrarily determined by the system, it is easy to add or change abnormal conditions, and it is possible to flexibly detect and display abnormal conditions. becomes. Furthermore, it is also possible to detect and display various abnormal states created by software that are not caused by hardware.

[Brief explanation of drawings]

FIG. 1 is an example of a conventional system, FIG. 2 is a configuration of an embodiment of the present invention, FIG. 3 is a diagram for explaining an example of an abnormal condition, and FIG. 4 is an example of an abnormal setting state storage unit shown in FIG. 2. FIG. 5, which is a diagram for explanation, shows a process explanatory diagram of an embodiment of the present invention. In the figure, 1 is a central processing unit, 10 is a service processor, 13 is a scanout circuit, and 14-1
14-3 is a latch, 16 is a scan-out address register, 17 is an in-gate register, 19 is a condition setting section, 20 is an abnormal setting state storage section, 22 is an address setting section, 23 is an internal state detection section, 24 is an abnormal state determination unit; 2
5 represents an abnormal state display section.

Claims (1)

[Claims] 1 Services that operate and control the system
In a system equipped with a processor and a scan-out circuit that reads and collects the internal state of the hardware of each device, there is a condition setting section that presets conditions to be reported as an abnormal state of the system, and an address setting section that sets a scanout address assigned to hardware corresponding to the specified condition in a scanout address register; and an internal state extracted by the scanout address set in the address setting section. an internal state detection unit that reads out the
an abnormal state determining section that determines whether or not the state detected by the internal state detecting section or the state forcibly set by the operation command corresponds to a condition preset in the condition setting section; 1. An abnormality detection and display control method, comprising: an abnormal state display section that displays the determination result of the abnormal state determination section.