JPH0877069A - Cache testing method - Google Patents

Abstract

PURPOSE: To shorten the time required for product inspection by setting a diagnostic program in a cache memory at a time. CONSTITUTION: A microprocessor chip 1 is connected to an external test device 2 ab the time of production inspection which is done before shipment. The microprocessor chip 1 has a data processor 3 and the cache memory 4 inside and is connected by a control bus, an address bus, a data bus, etc., and provided with an internal register. Then process instructions stored in the cache memory 4 are fetched and executed in order. Namely, data can be written to and read out of all the addresses of the cache memory 4 without supplying access instructions to the data processor 3 in order. Further, data other than a defect detection signal need not be transferred between the data processor 3 and external test device 2 during the execution of the diagnostic program. The time required for the production inspection can, therefore, be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache test method for confirming a cache function in product inspection of a semiconductor chip in which a cache memory is incorporated with a data processor.

[0002]

2. Description of the Related Art Recent computer systems use a cache memory to improve the processing speed. This cache memory is a non-volatile memory such as SRAM which has an access time shorter than that of the main memory.
It is formed on the same semiconductor chip with a data processor such as U. The data processor collectively transfers processing instructions from the main memory to the cache memory for each predetermined number, and sequentially fetches and executes the processing instructions from the cache memory. The batch transfer of the processing instructions is extremely fast, and the ratio of the instruction fetch time to the entire processing time can be reduced as compared with the case of directly fetching the processing instructions from the main memory.

In the above-mentioned semiconductor chip product inspection, an external tester is connected to the semiconductor chip to perform a test for confirming the cache function. The external test device writes various data patterns to the cache memory via the data processor, reads the data patterns from the cache memory via the data processor, and compares the write data pattern with the read data pattern to cause a malfunction. Find out if there is.

[0004]

However, in this test method, the external test apparatus must supply the data processor with sequential access instructions for all addresses of the cache memory in writing and reading of each data pattern. Further, even if data is transferred at high speed between the cache memory and the data processor, it is difficult to transfer at high speed between the data processor and the external test equipment. Therefore, a lot of time is required for product inspection due to delay in detecting defects in the cache memory.

An object of the present invention is to provide a cache test method capable of reducing the time required for product inspection.

[0006]

According to the present invention, a step of setting a cache diagnostic program in a part of a cache memory formed in a semiconductor chip together with a data processor, and a diagnostic program stored in the cache memory A cache test method is provided that includes causing a processor to execute, and monitoring a failure detection signal obtained from a data processor when a failure of a cache function is detected by executing a diagnostic program.

[0007]

In this cache test method, the diagnostic programs are collectively set in the cache memory,
It becomes possible to perform data writing and data reading for all addresses of the cache memory without supplying sequential access instructions to the data processor. Furthermore, during execution of the diagnostic program, it is not necessary to transfer data other than the defect detection signal between the data processor and the external test equipment. Therefore, the time required for product inspection can be significantly reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A cache test method according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 schematically shows the structure of a semiconductor microprocessor chip 1 to which this cache test method is applied. The microprocessor chip 1 is connected to the external test device shown in FIG. 1 in a product inspection performed before shipping. The microprocessor chip 1 contains a data processor 3 and a cache memory 4. The processor 3 is connected to the cache memory 4 via a control bus, an address bus, a data bus, a tag valid line, etc., and sequentially fetches and executes the processing instructions stored in the cache memory 4. The data processor 3 is provided with n internal registers. The cache memory 4 is a non-volatile memory in which a plurality of static memory cells are arranged in a matrix, and an address is assigned to each predetermined number of memory cells. At each address, a predetermined number of memory cells form a plurality of data bits that store data such as a processing instruction, a plurality of tag bits that represent an index, and a valid bit that represents a rewrite attribute.

Next, a test process for confirming the cache function using the external test device 2 will be described. FIG. 2 is a flowchart of this test process. When this test process is started, the external test apparatus 2 sets the diagnostic program in the cache memory 4 in step S1. This diagnostic program is supplied from the external test apparatus 2 to the processor 3 and transferred to the diagnostic program area 4A formed by a part of the cache memory 4 via the processor 3.
In step S2, the external test apparatus 2 executes the diagnostic program stored in the diagnostic program area 4A on the processor 3
To run. Further, in step S3, the external test apparatus 2 monitors the defect detection signal obtained from the processor 3 when the cache function defect is detected.

The data processor 3 executes the diagnostic program to perform the cache diagnostic process shown in FIG. When the cache diagnosis process is started, the write data is stored in the first register of the processor 3 in step S10, and the test start address is stored in the second register of the processor 3 in step ST11. Step S12
Then, the content of the first register is written to the address of the cache memory 4 designated by the second register.
After that, the processor 3 increments the second register in step S13 to specify the next write address,
In step S14, it is checked whether the content of the second register exceeds the final address. If the final address is not exceeded, steps S12-14 are repeated. As a result, the contents of the first register are written in the cache register 3 in, for example, the entire address range excluding the diagnostic program area 4A. Thereafter, the test start address is stored in the second register again in step ST15, and the data is read from the address designated by the second register and stored in the third register of the processor 3 in step S16. The contents of this third register are set in step S1.
At 7, it is checked whether it matches the contents of the first register.
If they do not match, the processor 3 stores predetermined error data in the fourth register and ends the diagnostic process. The error data is supplied from the fourth register to the external test apparatus 2 as a defect detection signal.

On the other hand, if a match is detected in step S17, the second register is incremented in step S19 to specify the next read address. Step S1
At 4, it is checked if the contents of the second register exceeds the final address. If the final address is not exceeded, steps S16-20 are repeated. As a result, the contents of the first register are changed to the diagnostic program area 4
For example, in the entire address range except A, the read data read from the cache register 3 is sequentially compared.
When the content of the second register exceeds the final address, the diagnostic process ends.

According to the above-described embodiment, the diagnostic programs are collectively set in the cache memory 4 so that the data writing and the data reading can be performed without repeatedly supplying the access instruction of the cache memory 4 to the data processor. It will be possible. Further, during execution of the diagnostic program, it is not necessary to transfer data other than the defect detection signal between the data processor 3 and the external test device 2. Therefore, the time required for product inspection can be significantly reduced.

Although the diagnosis of the diagnostic program area 4A is omitted in this embodiment, the diagnostic program area 4A is a little smaller than the remaining areas. It can be almost detected when a region other than 4A is diagnosed. If diagnosis is performed for all addresses of the cache memory 4, it can be realized by changing the diagnostic program area 4A to another part of the cache memory 4.

The present invention is not limited to the above embodiment,
Various modifications can be made without departing from the spirit of the invention.

[0016]

According to the present invention, the product inspection can be completed in a shorter time.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a structure of a semiconductor microprocessor chip to which a cache test method according to an embodiment of the present invention is applied.

2 is a flowchart of a test process performed by the external test apparatus shown in FIG.

FIG. 3 is a flowchart of cache diagnosis processing in the processor shown in FIG.

[Explanation of symbols]

1 ... Semiconductor microprocessor chip, 2 ... External test device, 3 ... Data processor, 4 ... Cache memory,
4A ... Diagnostic program area.

Claims (1)

[Claims] 1. A step of setting a cache diagnostic program in a part of a cache memory formed in a semiconductor chip together with a data processor, a step of causing the data processor to execute the diagnostic program stored in the cache memory, and a cache. And a step of monitoring a failure detection signal obtained from the data processor when a failure of the function is detected by executing the diagnostic program.