1288242 九、發明說明： 【發明所屬之技術領域】 本發明係提供-種數位邏輯職方法(digital lGgic test method)，尤指一種以系統性地方式完整地測試一數位邏輯 晶片之所有功能之數位邏輯挪試方法。 【先前技術】 在個人電細剛走進豕庭的一九九〇年代初，六十四百萬 位70組記憶容Ϊ的動態隨機存取記憶體(DRAM)為個人電 腦中記憶體之主要規格，當時，一台個人電腦通常内含多 達六十至一百個雙列直插式封裝（dual in_line package，mp) 晶片，而VAX11/780為一種廣為邏輯設計人員（1〇gic designer)所用以設計晶片之電子設計自動化裝置 (electronic design automation，EDA)。隨著電子科技的高速 發展，如今的個人電腦中通常僅包含數個積體電路 (integrated circuit，1C)晶片，以節省製造成本，相應地，如 今之邏輯設計人員可使用更現代、功能更為強大之EDA裝 置來设计以往需要更多邏輯設计人貝通力合作方有能力設 計完成之積體電路晶片。 雖然包含較少之積體電路晶片，如今的個人電腦所具有 之功能相較於過往之個人電腦所具有之功能卻絲亳不遜 1288242 色，不問可知，每一積體電路晶片之内部電路一定較傳統 之雙列直插式封裝晶片之内部電路複雜許多。 然而，在電子科技高速發展的過程中，也不是一路都很 順遂而耄無問題的。舉例來說，積體電路晶片之發展往往 文制於數位邏輯測試方法(digital logic test method)之有效 與否。在典型的數位邏輯測試方法中，受控於硬體設計語 言（hardware design language，HDL)之模擬裝置（simuiator) 施加一測試模式（test pattern or test vector)至一受測裝置 (device under-test，DUT)之接腳，並藉由量測該DUT之測 試反應（response)與一預期反應間的差異之方式，判定該 DUT是否係正常運作著。積體電路晶片的内部電路之曰益 複雜化，並不必然地會伴隨著積體電路晶片的接腳數目之 增加，換言之，在積體電路晶片的接腳增加有限的情況下， 數位邏輯測試方法卻仍必需經由該DUT之接腳輸入更多 不同塑式的刺激(stimuli)，以測試該DUT所額外增加的功 能。因此，從完成一積體電路晶片所需的各種不同之過程 看來，邏輯測試人員（logic tester)所面臨的挑戰實不亞於邏 輯設計人員所面臨的挑戰，而一積體電路晶片之成本中屬 於數位邏輯測試之部分也漸漸地超越屬於邏輯設計之部分 了。更甚者，對於一些較為複雜而難以測試之積體電路晶 片之内部電路而s ’例如像是順序電路(sequential circuit) ’邏輯測試人員可能會反過頭來要求邏輯設計人員 1288242 減化該内部電路。因此，一些可同時兼顧邏輯設計與邏輯 測試之EDA裝置（design-for-test)便應運而生了，換言之， 邏輯設計人員於設計一積體電路晶片時，可同時考慮到未 來該積體電路晶片是否具有可測試性(testability)。 積體電路晶片中的瑕疵可能零星地出現在個別積體電 路晶片上，也可能系統性地出現在整批積體電路晶片中。 一般而言，零星地出現於個別積體電路晶片上之瑕疵（每一 積體電路晶片皆已達到公司所訂定之可接受品質標準 (acceptable quality level，AQL))尚不致於對製造該積體電 路晶片之公司造成任何信譽上的損傷，然而，若瑕疵係系 統性地出現在該公司所生產的整批積體電路晶片中的話， 情況就非同小可了，因此，數位邏輯測試方法不僅需找出、 更必需儘早地找出（至少要在該積體電路晶片出貨給客戶 之前）該積體電路晶片中的瑕疵。 近年來，各種用以測試積體電路晶片之數位邏輯測試方 法相繼地問市，例如像是邏輯暨錯誤模擬演算法(logic and fault simulation algorithm)、用以測試組合電路 (combinational circuit)之自動測試模式產生（automatic test pattern generation，ATPG)技術、用以測試順序電路之反覆 測試產生（iterative test generator，ITG)技術、以及用以測試 記憶體之躍步模式（GALloping PATtern，GALPAT)技術等。 1288242、 而針對其所施加於該DUT上之測試模型而言，這些數位邏 輯測試方法中較常為邏輯测試人員所應用的為功能涵蓋 (fimction coverage)及程式碼涵蓋（c〇de兩種。 以程式碼涵蓋為例，程式碼涵蓋之優點係在於其可輕易 地界定測試範圍、並可應用於暫存器轉換層次(register transfer level，RTL)。當錯誤(bug)出現時，程式碼涵蓋可立 即地暫時改正(correct)该rtl、並持續地進行測試。程式碼 涵蓋可用來量測區塊涵蓋(bl〇ck coverage)、表示式涵蓋 (expression coverage)、路徑涵蓋（path coverage)、以及專屬 於狀態機器（state machine)之分支涵蓋（branch coverage)等。 根據統計，由於邏輯設計人員不可能設計出能涵蓋程式 碼涵蓋所必需涵蓋之所有測試模型，因此，一般說來，程 式碼涵蓋之涵蓋率（effectiveness)約介於百分之八十（測試 較大的模組(module))至九十（測試較小的模組）之間，然 而’如此高的涵蓋率充其量僅能說明程式碼涵蓋所測試之 積體電路晶片具有較高的可靠性，但卻不能就此斷定該積 體電路晶片禮係完美而毫無瑕疲的。此外，程式石馬涵蓋也 無法找出隱存在於子模組(sub-module)間之錯誤。 功能涵蓋通常係用於積體電路晶片之初期測試 (preliminary test)中，以儘早地先找出積體電路晶片中之明 1288242 顯錯誤（gross deficiencies)。功能涵蓋係於一模擬裝置上執 行邏輯設計人員及邏輯測試人員依據一積體電路晶片之特 性所特別設計之測試模型，以測試該積體電路晶片。隨著 該積體電路晶片内所包含之如電晶體及暫存器等之電子元 件數目的增加，功能涵蓋於該模擬裝置上用以測試該積體 電路晶片所需之測試模型的數目也必隨之增加。 一個數位邏輯測試方法的好壞除了在於其所提供的測 試資訊可否精確地涵蓋一積體電路晶片中所有變數之可能 變化外，更重要的是，這些測試資訊必需很容易地便能獲 得。換言之，對於一個好的數位邏輯測試方法而言，除了 對於熟習該積體電路晶片之邏輯設計人員外，任何人皆應 可輕易地設計出對應於該積體電路晶片之測試模型，並於 該數位邏輯測試方法中執行該測試模型後，取得相關於該 積體電路晶片之測試貨訊。以功能涵盖為例’對於親自參 與設計一積體電路晶片之邏輯設計人員而言，完整地設計 出對應於該積體電路晶片之測試模型固不成問題(但仍可 能有所疏露），然而，對於那些沒有實地參與故未能確實熟 悉該積體電路晶片之邏輯測試人員而言，要求其也能完整 地設計出那些測試模型便有點強人所難了。 1288242 【發明内容】 因此本發明之主要目的在於提供一種以系統性地方式 完整地測試一數位邏輯晶片之數位邏輯測試方法，以解決 習知技術之缺點。 根據本發明之申請專利範圍，本發明係揭露一種數位邏 輯測试方法’其包含··提供可於同一時段内同時執行STAGE 個指令、並藉由循序地進行STAGE個具有不同特性的工作 段之方式，執行完畢每一指令之積體電路晶片；對該積體 電路晶片所能執行之指令加以分類；以及依據該積體電路 晶片之STAGE個工作段以及對該積體電路晶片所能執行 之指令之分類個數、設計用以於每一個對應於該STAGg個 工作段之測試段測試該積體電路晶片之測試模式。 在本發明之較佳實施例中，該數位邏輯測試方法另包 含：依據該積體電路晶片於該STAGE測試段所分別具有之 特別因素設計該測試模式。對應地，該測試模式之個數為 (NoITfTAG'f!* f2* f3* f4* fsTAGE)，其中 N〇IT 為該分類俩 數，而fSTAGE為該積體電路晶片於第STAGE測試段所具有 之特別因素之個數。 根據本發明之申請專利範圍，本發明另揭露一種用來測試〜 積體電路晶片之數位邏輯測試裝置，該積體電路晶片可於 10 1288242 同一時段内同時執行STAGE個指令、並藉由循序地進行 STAGE個具有不同特性的工作段之方式，執行完畢每一指 令，該數位邏輯測試裝置包含：一指令分類器，用來對該 積體電路晶片所能執行之指令加以分類、並據以產生一分 類個數；以及一測試模式產生器，用來依據該積體電路晶 片之STAGE個工作段以及該分類個數、產生用以於每一個 對應於該STAGE個工作段之測試段測試該積體電路晶片 之測試模式。 根據本發明之申請專利範圍，本發明另揭露一種數位邏 輯測試系統，其包含：一積體電路晶片，其可於同一時段 内同時執行STAGE個指令、並藉由循序地進行STAGE個 具有不同特性的工作段之方式，執行完畢每一指令；以及 一數位邏輯測試裝置，用來測試該積體電路晶片，而該數 位邏輯測試裝置包含：一指令分類器，用來對該積體電路 晶片所能執行之指令加以分類、並據以產生一分類個數； 以及一測試模式產生器，用來依據該積體電路晶片之 STAGE個工作段以及該分類個數、產生用以於每一個對應 於該STAGE個工作段之測試段測試該積體電路晶片之測 試模式。 由於本發明之數位邏輯測試方法係循序地依據一積體 電路晶片之所有功能於執行時所必需經歷之各種具有不同 1288242 特性之工作段測試該積體電路晶片之所有功能，所以，本 發明之數位邏輯測試方法可完整地測試該積體電路晶片之 所有功能。 【實施方式】 為了提昇執行指令之效率，現今之處理器（所有積體電路 晶片中運作最為複雜的一種積體電路晶片）大都為採用管 線結構(pipeline structure)之多指令单資料流糸統(multiple instruction stream single data stream system，MISD)，以於同 一時段内能同時執行複數個指令。一般而言，具有管線結 構之處理器係將一指令週期（instruction cycle)分解為循序 進行的五個分別具有不同特性之工作段：一讀取指令(fetch) 工作段(operation segment)、一解碼(decode)工作段、一執 行（execute)工作段、一記憶體存取(memory access)工作段、 以及〆寫回（write back)工作段（亦可分解成一讀取指令工 作段、一解碼工作段、一讀取運算元(0Perand read)工作段、鲁 /執行工作段、以及一寫回工作段、或一讀取指令工作段、 〆讀取運算元工作段、一執行工作段、一記憶體存取工作 段、以及一運算元儲存工作段）。該五種工作段皆分配到等 長之工作時間，該處理器内之執行單元（execution unit，EXU) <以重疊（overlaP)的方式解碼並執行一程式(program)中所 包含之指令。相應地，本發明之數位邏輯測試方法係循序 地依據一積體電路晶片之所有指令於執行時所必需經歷之 12 1288242 各種不同工作段測試該積體電路晶片。請參閱第1圖，第 1圖為本發明之較佳實施例中一數位邏輯測試方法100之 流程圖。數位邏輯測試方法100包含一讀取指令測試段 (F)102、一解碼測試段(D)104、一執行測試段(E)106、一記 憶體存取測試段(M)108、以及一寫回測試段(W)110。 該處理器内之執行單元通常包含一（單埠或多埠)通用暫 存器模組（general purpose register module，GPR)、一 特定用 途暫存器模組(special purpose register module, SPR)、一算 術邏輯單元(ALU)、一乘法器、一除法器、以及一用以控制 資料流（data flow)及指令執行（instruction execution)之控制 邏輯單元(control logic unit)。該特定用途暫存器模組可包 含一用以儲存下一個待執行指令的位址之程式計數器 (program counter，PC)、一用以儲存正在執行的指令之指令 暫存器、一用以指示待存取資料（或運算元）記憶體的位址 之位址暫存器（可包含一記憶體位址暫存器（mein〇ry address register，MAR))、一狀態暫存器、以及一用以儲存 一堆疊頂端的位址之堆疊指標暫存器。該執行單元除了可 以重疊的方式解碼並執行一程式中所包含之指令外，另可 處理諸如佇列管理（queue management)及分支預測（branch prediction)等工作。 該處理器所能執行的指令依據執行完畢後是否將一新 13 1288242 的指令位址（instruction address)儲存至該程式計數器而可 分為分支指令(branch instruction)、以及資料處理指令(data processing instruction)兩大類’前者如指定（assignment)、假 定(IF)、及呼叫（call)等，而後者又可細分為M〇v、ADD、 DIV、MUL、LDR、及STR等。該處理器内之執行單元於 該解碼工作段所解碼而得之指令若為一分支指令，該執行 單元必需回到該解碼工作段前之讀取指令工作段讀取該分 支指令所指示之指令，換言之，循序地執行指令㈣職_ execution of instruction)之規則會被打破。 該處理器於執行該等指令時，會分別牵涉到不同的硬體 構件。舉例來說，錢處理器内之執行單元所執行之指人 為讀Rx，m(記憶體資料搬移’由記憶體的某一位址將; ^讀出，再存人該處理器之某—暫存器内），該執行單^ 先將所要讀取之位址送至該記憶體位址暫存器；^ ，理器發出—讀取信號；最後，該處理器將所讀得之資;； 存入該暫存器内。換言之，該處理 、4 會牽涉到該記憶體位址暫存器等硬體構^膽指令時’ 因此，本發明之數位邏輯測試方法 積體電路晶片（該處理器）之所有指令於勃」“地依據— 之各種不同工作段測試該處理器外，一寺斤必舄經歷 行該等指令時所牽涉到之硬體構件之=據該處理器於執 +同將該等指令分 1288242 成複數種指令型式（instruction type)。 請參閱第2圖，第2圖列出數位邏輯測試方法1〇〇所測 試之處理器於執行一程式時、該程式所包含之複數個指令 及該等指令所屬之指令型式。不同指令型式之指令於被該 處理器執行時，會牽涉到不同的硬體構件。假設該處理器 所能執行之指令所屬之指令型式僅為第2圖中所顯示之六 種’也就是指令型式編號從，，〇，，到”5，，之ALU!、Load、ALU2、 Multiplier、Branch、及 ST〇RE。 請參閱第3圖，第3圖為第1圖所顯示之數位邏輯測試 方法100於執行第2圖所顯示之程式時之時序圖。在第3 圖中’就<壬一指令而言，例如BNE0xl00(Branch，n+7)，數 位邏輯測試方法100皆必需依序於五個連續之時間點（例如 時間點丁4至τ8)對其執行上述之五種測試段·· F、D、E、 Μ、及W，另一方面，就任一時間點而言，例如一第一時 間點Τ!，數位邏輯測試方法1〇〇係對該程式中五個連續之 指令，例如 ADD rl，r2，r3(ALU，n)、LDR r2，[r6]，#4(Load， n+1)、MOV rO，r2，LSL#0(ALU，n+2)、MOV rl，r2，LSL#1 (ALU，n+3)、及 MULrO，rl，rO(Multiplier，N+4)分別執行 W、Μ、E、D、及F五種測試段。 從第3圖可看出’由於每一指令皆必需經過五種測試 1288242 段、而每一種測試段皆可有六種不同的指令選擇，所以， 數位邏輯測試方法100所選取之施加至一受測裝置的接腳 之測試模式便有（6*6*6*6*6)=NoITstage種組合，其中 STAGE為具有管線結構之處理器於同一工作段内所能執行 的才日々之個數’而NoIT(number of instruction type)為該處 理器所能執行之指令所屬之指令型式之個數，即便二相鄰 受測模式所對應之指令間存在有資料依附（data dependency) 的問題。 由&處理器（執行單元)執行指令所需耗費的時間遠小於 存取一A憶體所需耗費的時間，因此，為了增加執行程式 之效率’現今之處理器率皆配置有一第一級快取記憶體(Li cache memory) ’以加速存取記憶體之速率。依據儲存内容 種類之不同’第一級快取記憶體可分為用以儲存指令之指 令快取單凡（mstructi〇n cache unh，ICU)、以及用以儲存資 料之二貝料快取單元(data cache unit，DCU)兩種。一般而言，籲 每一快取記憶體皆包含一快取控制 器(cache controller)、一 通书為一靜怨隨機存取記憶體(SRAM)之資料陣列(data array)、以及一標記（tag)。該標記係用來記錄該SRAM内之 貝料於❼亥主吕己憶體内之位址，該快取控制器係於處理器需 要存取主記憶體内的資料(指令）時，藉由比較該資料的位 址與礼，己的内容之方式，判定該内是(命中⑽)） 否（失誤(miss))儲存有該資料。舉例來說 ，若該快取控制器 16 1288242 判定該處理器所欲執4亍之4曰令係儲存於該資料陣列中（命 中），該快取控制器將儲存於該資料陣列中之指令傳送至該 執行單元内之佇列，反之，若該快取控制器判定該資料陣 列中並未有該處理器所欲執行之指令（失誤），該快取控制 器便透過一匯流排介面單元(bus interface unit)從外接於該 處理器之記憶體（可能為一第二級快取記憶體或一主記憶 體)攫取(fetch)該指令。 上述之快取記憶體係為了辅助主記憶體資料存取速率 不快而設置的，另一方面，一處理器可藉由存取一虛擬記 憶體(virtual memory)内資料之方式，克服主記憶體資料儲 存容量不足之缺點。該處理器可藉由讀取一轉換表緩衝區 (translation look-aside buffer, TLB)内頁數(page)之方式（由 该處理器内之§己憶體管理單元（mem〇ry management un^， MMU)所管理，其可將一邏輯位址(i〇gic “心⑵勾與一實體 位址(physical address)互換），判定於執行程式時是（頁命中 (TLB page hit))否（分頁失效(TLB page faul〇)需作頁的轉 換。同樣地，TLB依據儲存内容之不同，可分為指令轉換 表緩衝區（ITLB)及資料轉換表緩衝區（DTLB)兩種。 在忒扎令週期之頃取指令工作段時，該處理器中之執行 單兀(與該記憶體管理單元共同運作）會先將一待執行指令 的位址由遠程式計數器送至該記憶體位址暫存器；接著， 17 1288242 該處理器發出一讀取信號、並修改該程式計數器之值，使 其指向下一個待執行指令的位址；最後，該處理器將所讀 取到的指令由該記憶體資料暫存器送到該指令暫存器，以 備解碼（該解碼工作段）。 該處理器所讀取到之指令可能原本係儲存於該指令快 取單元、该主記憶體、或該虛擬記憶體内，端視，，快取命中 (icuhit)’’或”快取失誤(ICUmissed)，，、以及，，頁命中（ITLB Page hit)”或”分頁失效(ITLB page fault)”而定。相應地，數· 位邏輯測試方法100之讀取指令測試段1〇2便可依據，，快取 命中”或”快取失誤，，、以及，，頁命中，，或，，分頁失效，，來測試運 作於該讀取指令工作段時之處理器。舉例來說，（丨）若，，快取 失疾’代表該處理器於該讀取指令工作段時並無法從該指 令快取單元内讀取到該指令，所以，接下來應測試，，頁命中，， 及分頁失效”；（la)若”頁命中，，，代表該處理器於該讀取指 令工作段時可從該主記憶體内讀取到該指令；（lb)反之，參 若i頁失效’’代表該指令只要可能儲存於該虛擬記憶體 内’若該處理器仍無法從該虛擬記憶體内找到該指令，代 表該處理器於讀取該指令時發生錯誤；（2)另一方面，若一 開始便’’快取命中，，，代表該處理器於該讀取指令工作段時 已從該指令快取單元内讀取到該指令，所以，該處理器便 無需另從該主記憶體或該虛擬記憶體内找尋該指令了，也 就是無需再測試，，頁命中，，及，，分頁失效，，了。 18 1288242 對應地’數位邏輯测試方法1〇〇於測試該處理器時，也 可因該處理n时無配置該虛擬記憶體、該資料快取單 及該指令快取單元而異其測試模式。簡言之，數位邏 輯測试方法1GG於各個測試段，除了可依據該處理器所能 執灯之指令所屬之指令型式設計測試模型外，尚可另依據 該處理器於該測試段所具有之特別因素而增加測試模型之 口月參閱第4圖’第4圖為數位邏輯測試方法1〇〇中將讀 取才曰1測5式段1〇2中之指令快取單元命中/失誤(ICU hit/miss)之特別因素一併加以考慮後所得之測試模式。承第 3圖之例，數位邏輯測試方法1〇〇所選取之施加至一受測 裝置的接腳之測試模式可有（(6*2)* (6*2)* (6*2)* (6*2)* (6*2))= (NoIT*f1)*(NoIT*f2)*(NoIT*f3)*(N〇IT*f4) (麗T*fSTAGE)=(No时_*(fi* f2* f3* f4* 其中STAGE為具有管線結構之處理器於同一工作段内所 能執行的指令之個數，NoIT為該處理器所能執行之指令所 屬之指令型式之個數，而fSTAGE為該處理器於第STAGE測 試段所具有之特別因素之個數。 請參閱第5圖，第5圖為本發明數位邏輯測試系統5〇〇 之示意圖。數位邏輯測試系統500係用來實現以上所述之數位邏 19 1288242 輯測試方法。數位邏輯測試系統，包含―積體電路晶片观及 —數位邏輯測試裝置5〇4，用來測試積體電路晶片观。積體電路 晶片502包含-指令快取單元51〇, 一資料快取單元512及一纪憶 體管理單元5H，且積體電路晶請可於同1段内同時齡 STAGE個指令、並藉由循序地進行STAGE個具有不同特性的工 作段之方式，執行完畢每一指令。 數位邏輯測試裝置504包含-指令分類器5〇6,用來對積體電_ 路曰曰片502所月b執行之指令力口以分類、並據以產生一分類^^固數， 及測5式模式產生器508，用來依據積體電路晶片5〇2之stage 個工作段以及該分類個數、產生用以於每一個對應於該stage個 工作段之測試段測試積體電路晶片5〇2之測試模式。測試模式產 生器508可產生NoITSTAGE個測試模式，其中N〇IT為該分類個 數。除此之外，測試模式產生器5〇8可依據積體電路晶片5〇2於 該STAGE測試段所分別具有之特別因素，產生用以於每一個對應❿ 於該STAGE個工作段之測試段測試該積體電路晶片之測試模 式’而該測試模式之個數為(N〇iT)STAGE*(fl*f2*f3*f4* fSTAGE) ’其中ΝοΓΓ為該分類個數，而βΤΑ(}Ε為該積體電路晶 片於第STAGE測試段所具有之特別因素之個數。 相較於習知數位邏輯測試方法，本發明之數位邏輯測試 方法係循序地依據一積體電路晶片之所有功能於執行時所 20 !288242 必需經歷之各種不同工作段測試該積體電路晶片，並且， 該數位邏輯測試方法另依據該處理器於各個測試段所具有 之特別因素設計該測試模式，所以，本發明之數位邏輯測 試方法可有系統地測試一積體電路晶片。換言之，本發明 之數位邏輯測試方法之涵蓋率明顯地高於習知程式碼涵蓋 之涵蓋率。 【圖式簡單說明】1288242 IX. Description of the Invention: [Technical Field of the Invention] The present invention provides a digital lGgic test method, and more particularly a system for completely testing the digital functions of all functions of a digital logic chip in a systematic manner. Logical test method. [Prior Art] At the beginning of the 1990s, 64 million 70-memory dynamic random access memory (DRAM) was the main memory of personal computers. Specifications, at the time, a personal computer usually contained up to sixty to one hundred dual in-line package (mp) chips, while the VAX11/780 was a widely used logic designer (1〇gic designer) The electronic design automation (EDA) used to design the wafer. With the rapid development of electronic technology, today's personal computers usually only contain several integrated circuit (1C) chips to save manufacturing costs. Accordingly, today's logic designers can use more modern and more functional. Powerful EDA devices are designed to design integrated circuit chips that have previously required more logic designers to work with. Although it contains a small number of integrated circuit chips, today's personal computers have functions that are comparable to those of previous personal computers. However, the internal circuits of each integrated circuit chip must be compared. The internal circuitry of conventional dual in-line packaged chips is much more complicated. However, in the process of rapid development of electronic technology, it is not all the way to go smoothly and without problems. For example, the development of integrated circuit chips is often written in the validity of the digital logic test method. In a typical digital logic test method, a simulation device controlled by a hardware design language (HDL) applies a test pattern or test vector to a device under test. , DUT) pin, and determine whether the DUT is functioning normally by measuring the difference between the test response of the DUT and an expected reaction. The complexity of the internal circuit of the integrated circuit chip is not necessarily accompanied by an increase in the number of pins of the integrated circuit chip, in other words, in the case where the number of pins of the integrated circuit chip is limited, the digital logic test The method still has to input more different plastic stimuli via the pins of the DUT to test the additional functions of the DUT. Therefore, from the various processes required to complete an integrated circuit chip, the logic tester faces the same challenges as logic designers, and the cost of an integrated circuit chip. The part of the digital logic test is gradually surpassing the part of the logic design. What's more, for some internal circuits of complex circuit chips that are difficult to test, such as, for example, a sequential circuit, the logic tester may reverse the need to require the logic designer 1288242 to reduce the internal circuit. . Therefore, some EDA devices that can simultaneously take into account both logic design and logic testing have emerged. In other words, logic designers can consider the integrated circuit in the future when designing an integrated circuit chip. Whether the wafer has testability. The defects in the integrated circuit chip may appear sporadically on the individual integrated circuit wafers, or may systematically appear in the entire batch of integrated circuit chips. In general, sporadic occurrences on individual integrated circuit chips (each integrated circuit chip has reached the acceptable quality level (AQL) set by the company) is not yet suitable for manufacturing the integrated body. The company of circuit chips causes any reputational damage. However, if the system is systematically present in the entire batch of integrated circuit chips produced by the company, the situation is not trivial. Therefore, the digital logic test method not only needs to find out It is even more necessary to find out (at least before the integrated circuit chip is shipped to the customer) the defects in the integrated circuit chip. In recent years, various digital logic test methods for testing integrated circuit chips have been successively asked, such as, for example, logic and fault simulation algorithms, automatic tests for testing combinational circuits. Automatic test pattern generation (ATPG) technology, an iterative test generator (ITG) technique for testing sequential circuits, and a GALloping PATtern (GALPAT) technique for testing memory. 1288242, and for the test model applied to the DUT, these digital logic test methods are more commonly used by logic testers for functional coverage and code coverage (c〇de) Taking code coverage as an example, the advantage of the code is that it can easily define the test range and can be applied to the register transfer level (RTL). When a bug occurs, the code Coverage can immediately correct the rtl and continue testing. Code coverage can be used to measure coverage coverage, expression coverage, path coverage, And branch coverage that is specific to the state machine, etc. According to statistics, because the logic designer cannot design all the test models that are required to cover the code coverage, in general, the code The coverage coverage is about 80% (testing larger modules) to 90% (testing smaller modules) However, 'such a high coverage rate can only indicate that the code covers the high reliability of the integrated circuit chip tested, but it cannot be concluded that the integrated circuit chip is perfect and not exhausted. The program stone can't find the error that exists between the sub-modules. The function covers usually used in the preliminary test of the integrated circuit chip to find the product as early as possible. The bulk deficiencies in the bulk circuit chip. The function covers the test model specially designed by the logic designer and the logic tester according to the characteristics of an integrated circuit chip on an analog device to test the integrated body. a circuit chip. As the number of electronic components such as a transistor and a register included in the integrated circuit chip increases, the function covers the test model required for testing the integrated circuit chip on the analog device. The number will also increase. The good or bad of a digital logic test method is whether the test information provided can accurately cover an integrated battery. In addition to the possible variations of all the variables in the wafer, more importantly, these test information must be readily available. In other words, for a good digital logic test method, in addition to the logic designer who is familiar with the integrated circuit chip. In addition, any one should be able to easily design a test model corresponding to the integrated circuit chip, and after performing the test model in the digital logic test method, obtain a test cargo related to the integrated circuit chip. The function covers as an example. For a logic designer who personally participates in designing an integrated circuit chip, it is not a problem to completely design a test model corresponding to the integrated circuit chip (but it may still be exposed), however, For those logic testers who have not been involved in the field and are not really familiar with the integrated circuit chip, it is a little difficult to require them to design the test models completely. 1288242 SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a digital logic test method for systematically testing a digital logic chip in a systematic manner to address the shortcomings of the prior art. According to the scope of the patent application of the present invention, the present invention discloses a digital logic test method that includes providing a STAGE instruction that can execute simultaneously in the same time period and sequentially performing STAGE work segments having different characteristics. a method of performing an integrated circuit of each instruction; classifying instructions executable by the integrated circuit chip; and performing STAGE working segments of the integrated circuit chip and performing on the integrated circuit chip The number of instructions is designed to test the test mode of the integrated circuit chip for each test segment corresponding to the STAGg working segments. In a preferred embodiment of the present invention, the digital logic test method further includes: designing the test mode according to a special factor of the integrated circuit chip in the STAGE test segment. Correspondingly, the number of test modes is (NoITfTAG'f!* f2* f3* f4* fsTAGE), where N〇IT is the number of the classification, and fSTAGE is the integrated circuit chip in the STAGE test segment. The number of special factors. According to the patent application scope of the present invention, the present invention further discloses a digital logic test device for testing a ~-integrated circuit chip, which can simultaneously execute STAGE instructions in the same time period of 10 1288242, and sequentially Performing each instruction in the STAGE work segments having different characteristics, the digital logic test device includes: an instruction classifier for classifying the instructions executable by the integrated circuit chip and generating accordingly a number of classifications; and a test pattern generator for testing the product according to the STAGE working segments of the integrated circuit chip and the number of the classifications, and generating test segments corresponding to each of the STAGE working segments The test mode of the body circuit chip. According to the patent application scope of the present invention, the present invention further discloses a digital logic test system, comprising: an integrated circuit chip, which can simultaneously execute STAGE instructions in the same time period, and sequentially perform STAGE with different characteristics. a working segment manner, each instruction is executed; and a digital logic testing device for testing the integrated circuit chip, and the digital logic testing device includes: an instruction classifier for the integrated circuit chip The executable instructions are classified and generated to generate a classification number; and a test pattern generator is configured to generate, according to the STAGE working segments of the integrated circuit chip and the number of the classifications, each of which corresponds to The test segment of the STAGE working segment tests the test mode of the integrated circuit chip. Since the digital logic test method of the present invention sequentially tests all functions of the integrated circuit chip according to various working segments having different characteristics of 1288242 that must be experienced during execution of all functions of an integrated circuit chip, the present invention The digital logic test method can completely test all the functions of the integrated circuit chip. [Embodiment] In order to improve the efficiency of executing instructions, today's processors (the most complex integrated circuit chip in all integrated circuit chips) are mostly multi-instruction single-stream systems using pipeline structures ( Multiple instruction stream single data stream system (MISD), so that multiple instructions can be executed simultaneously in the same time period. Generally, a processor having a pipeline structure decomposes an instruction cycle into five sequentially working segments having different characteristics: a read instruction (fetch), an operation segment, and a decoding. (decode) work segment, an execute work segment, a memory access work segment, and a write back work segment (which can also be decomposed into a read instruction work segment, a decoding job) Segment, a read operand (0Perand read) work segment, Lu/execution work segment, and a write back work segment, or a read instruction work segment, a read operand work segment, an execution work segment, a memory The body access working segment, and an operand storage working segment). The five working segments are all assigned to the same working time, and the execution unit (EXU) in the processor decodes and executes the instructions contained in a program in an overlaP manner. Accordingly, the digital logic test method of the present invention sequentially tests the integrated circuit chip according to various operating segments of 12 1288242 which must be experienced in execution of all instructions of an integrated circuit chip. Please refer to FIG. 1. FIG. 1 is a flow chart of a digital logic test method 100 in accordance with a preferred embodiment of the present invention. The digital logic test method 100 includes a read command test segment (F) 102, a decode test segment (D) 104, an execution test segment (E) 106, a memory access test segment (M) 108, and a write Return to test segment (W) 110. The execution unit in the processor usually includes a (單埠 or more) general purpose register module (GPR), a special purpose register module (SPR), and a special purpose register module (SPR). An arithmetic logic unit (ALU), a multiplier, a divider, and a control logic unit for controlling data flow and instruction execution. The specific purpose register module can include a program counter (PC) for storing an address of the next instruction to be executed, an instruction register for storing the instruction being executed, and a An address register of an address of the data (or operand) to be accessed (which may include a mein〇ry address register (MAR)), a state register, and a use A stack indicator register that stores the address of a stack top. In addition to decoding and executing the instructions contained in a program in an overlapping manner, the execution unit can handle tasks such as queue management and branch prediction. The instructions executable by the processor can be divided into branch instructions and data processing instructions according to whether a new 13 1288242 instruction address is stored in the program counter after execution. The two categories 'the former are assignment, hypothesis (IF), and call, etc., while the latter can be subdivided into M〇v, ADD, DIV, MUL, LDR, and STR. If the instruction decoded by the execution unit in the processor is a branch instruction, the execution unit must return to the read instruction working segment before the decoding working segment to read the instruction indicated by the branch instruction. In other words, the rules of the execution of instructions will be broken. When the processor executes these instructions, different hardware components are involved. For example, the execution unit executed by the execution unit in the money processor reads Rx,m (memory data transfer 'by a certain address of the memory; ^ read, and then save the processor some one - temporarily In the memory, the execution unit first sends the address to be read to the memory address register; ^, the processor issues a read signal; finally, the processor reads the capital; Stored in the scratchpad. In other words, the processing, 4 will involve the hardware address register such as the memory address register. Therefore, the digital logic test method of the present invention integrates all the instructions of the circuit chip (the processor). The test is based on the various working segments of the system, and the hardware components involved in the execution of the instructions are: according to the processor, the instructions are divided into 1,288,242. Instruction type. Please refer to Figure 2, Figure 2 shows the digital logic test method. The processor tested has a plurality of instructions and the instructions of the program when executing a program. The instruction type of different instruction types will involve different hardware components when executed by the processor. It is assumed that the instruction type that the processor can execute is only the six types shown in the second figure. 'That is the instruction type number from ,, 〇, to 5, ALU!, Load, ALU2, Multiplier, Branch, and ST〇RE. Please refer to FIG. 3, which is a timing diagram of the digital logic test method 100 shown in FIG. 1 when the program shown in FIG. 2 is executed. In the figure 3, in the case of 'an instruction, such as BNE0xl00 (Branch, n+7), the digital logic test method 100 must be sequenced at five consecutive time points (for example, time points D4 to τ8). Execute the above five test segments F·D, E, Μ, and W, on the other hand, for any time point, for example, a first time point Τ!, digital logic test method Five consecutive instructions in the program, such as ADD rl, r2, r3 (ALU, n), LDR r2, [r6], #4 (Load, n+1), MOV rO, r2, LSL#0 (ALU , n+2), MOV rl, r2, LSL#1 (ALU, n+3), and MULrO, rl, rO (Multiplier, N+4) perform five tests of W, Μ, E, D, and F, respectively. segment. As can be seen from Figure 3, since each instruction must pass through five tests of 1288242 segments, and each test segment can have six different instruction selections, the digital logic test method 100 is selected to apply to one The test mode of the test device's pin is (6*6*6*6*6)=NoITstage combination, where STAGE is the number of days that can be executed by the processor with pipeline structure in the same working segment. The No. (number of instruction type) is the number of instruction types to which the instructions executable by the processor belong, even if there is a problem of data dependency between the instructions corresponding to the two adjacent test modes. The time it takes to execute an instruction by the & processor (execution unit) is much less than the time it takes to access an A memory. Therefore, in order to increase the efficiency of the execution program, the current processor rate is configured with a first level. Cache memory (Li cache memory) 'to speed up access to memory. Depending on the type of storage content, the first-level cache memory can be divided into instructions for storing instructions, mstructi〇n cache unh (ICU), and two-material cache unit for storing data. Data cache unit, DCU). Generally speaking, each cache memory includes a cache controller, a data array of a random random access memory (SRAM), and a tag (tag). ). The mark is used to record the address of the shell in the SRAM in the body of the main memory, the cache controller is when the processor needs to access the data (instruction) in the main memory by Compare the address of the data with the manner of the gift, the content of the content, and determine whether the data is stored (hit (10))) (miss). For example, if the cache controller 16 1288242 determines that the processor is to be stored in the data array (hit), the cache controller will store the instructions stored in the data array. Transfer to the queue in the execution unit. Conversely, if the cache controller determines that there is no instruction (missing) to be executed by the processor in the data array, the cache controller passes through a bus interface unit. (bus interface unit) fetching the instruction from a memory external to the processor (possibly a second level cache or a main memory). The above-mentioned cache memory system is provided to assist the main memory data access rate is not fast. On the other hand, a processor can overcome the main memory data by accessing data in a virtual memory (virtual memory). The shortcomings of insufficient storage capacity. The processor can read the number of pages in a translation look-aside buffer (TLB) (by the processor in the processor) (mem〇ry management un^ , MMU), which can refer to a logical address (i〇gic "heart (2) hook and a physical address (physical address)), whether it is (TLB page hit) when executing the program ( Page breaks (TLB page faul〇) need to be converted. In the same way, TLB can be divided into two types: instruction conversion table buffer (ITLB) and data conversion table buffer (DTLB). When the cycle is taken from the instruction working segment, the execution unit in the processor (cooperating with the memory management unit) first sends the address of an instruction to be executed from the remote counter to the memory address temporary storage. Next, 17 1288242 the processor issues a read signal and modifies the value of the program counter to point to the address of the next instruction to be executed; finally, the processor reads the read instruction from the memory The data buffer is sent to the instruction register For decoding (the decoding working segment). The instruction read by the processor may be stored in the instruction cache unit, the main memory, or the virtual memory, end view, and cache hit. (icuhit) '' or 'cache misses (ICUmissed),, and, page hits (ITLB Page hit) or "ITLB page fault". Accordingly, the number bit logic test method 100 The read command test segment 1〇2 can be based on, the cache hit "or" cache miss,, and, page hit, or,, page break, to test the operation of the read instruction segment The processor of the time. For example, if (,), the cache misses 'represents that the processor cannot read the instruction from the instruction cache unit during the read instruction working segment, so Down, should test, page hit, and page break"; (la) If the "page hit,", the processor can read the instruction from the main memory in the read instruction working segment; Lb) Conversely, if the i page fails, '' represents the instruction as long as possible Stored in the virtual memory 'If the processor still cannot find the instruction from the virtual memory, it means that the processor has an error when reading the instruction; (2) on the other hand, if it starts, '' The cache hit, on behalf of the processor, has read the instruction from the instruction cache unit during the read instruction working segment, so the processor does not need to further access the main memory or the virtual memory. Look for the instruction inside, that is, no need to test again, page hit, and,, page break invalid,. 18 1288242 Correspondingly, the 'digital logic test method 1' is also suitable for testing the processor. When the n is processed, the virtual memory, the data cache, and the instruction cache unit are not configured, and the test mode is different. In short, the digital logic test method 1GG is used in each test segment, except that the test model can be designed according to the command type to which the processor can execute the command, but the processor can also be based on the test segment. Special factors and increase the test model's mouth month refer to Figure 4' Figure 4 is the digital logic test method 1〇〇 will read the test 1 test 5 type segment 1〇2 instruction cache unit hit / error (ICU Hit/miss) The special factors that are considered together are the test patterns. In the example of Figure 3, the test mode of the digital logic test method selected for the pin applied to a device under test may be ((6*2)* (6*2)* (6*2)* (6*2)* (6*2))= (NoIT*f1)*(NoIT*f2)*(NoIT*f3)*(N〇IT*f4) (丽T*fSTAGE)=(No time_* (fi* f2* f3* f4* where STAGE is the number of instructions that can be executed by the processor with the pipeline structure in the same working segment, and NoIT is the number of instructions that the processor can execute. fSTAGE is the number of special factors that the processor has in the STAGE test segment. Please refer to Figure 5, which is a schematic diagram of the digital logic test system of the present invention. The digital logic test system 500 is used. The above described digital logic 19 1288242 test method is implemented. The digital logic test system includes an integrated circuit chip view and a digital logic test device 5〇4 for testing the integrated circuit chip view. The integrated circuit chip 502 includes - an instruction cache unit 51A, a data cache unit 512 and a memory management unit 5H, and the integrated circuit crystals can be simultaneously STAGE instructions in the same segment, and sequentially Each instruction is executed in the manner of STAGE work segments having different characteristics. The digital logic test device 504 includes an instruction classifier 5〇6 for executing instructions on the month b of the integrated circuit 502. The force port is classified and generated to generate a classification ^^ solid number, and the 5 pattern generator 508 is used to generate the stage according to the stage working segments of the integrated circuit chip 5〇2 and the number of the classification. Each of the test segments corresponding to the stage working segments tests the test mode of the integrated circuit chip 5〇 2. The test pattern generator 508 can generate NoITSTAGE test patterns, where N〇IT is the number of the classification. The test pattern generator 5〇8 can generate the test body for each test segment corresponding to the STAGE work segment according to the special factor of the integrated circuit chip 5〇2 in the STAGE test segment. The test mode of the circuit chip 'and the number of the test mode is (N〇iT)STAGE*(fl*f2*f3*f4* fSTAGE) 'where ΝοΓΓ is the number of the classification, and βΤΑ(}Ε is the integrated body The special factors of the circuit chip in the STAGE test section Compared with the conventional digital logic test method, the digital logic test method of the present invention tests the integrated body in sequence according to various functions of an integrated circuit chip in accordance with various functions of an integrated circuit chip. The circuit chip, and the digital logic test method further designs the test mode according to the special factors of the processor in each test segment. Therefore, the digital logic test method of the present invention can systematically test an integrated circuit chip. In other words, the coverage of the digital logic test method of the present invention is significantly higher than the coverage covered by conventional code. [Simple description of the map]
第1圖本發明之較佳實施例中一數位邏輯測試方法之 流程圖。 第2圖列出第1圖所顯示之數位邏輯測試方法所測試 ，處理器於執行—程式時、該程式所包含之複數個指令及 该等指令所屬之指令型式。 第圖為第1圖所顯示之數位邏輯測試方法於執行第2 圖所顯示之程式時之時序圖。 奸H圖為第1圖所顯示之數位邏輯測試方法中將一讀 取“測試段中之指令快取單 之特別因素一併加以去“ r/^^(icu hit/miss) 考慮後所得之測試模式。 第5圖為本發日歧位邏胸試系統之示意圖。 21 1288242 【主要元件符號說明】 500數位邏輯測試系統 504數位邏輯測試裝置 508測試模式產生器 512資料快取單元 502積體電路晶片 506指令分類器 510指令快取單元 514記憶體管理單元BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a flow chart of a digital logic test method in accordance with a preferred embodiment of the present invention. Figure 2 shows the digital logic test method shown in Figure 1. When the processor executes the program, the program contains a plurality of instructions and the instruction type to which the instructions belong. The figure is a timing diagram of the digital logic test method shown in Figure 1 when executing the program shown in Figure 2. The rape H picture is the digital logic test method shown in Figure 1. The result of reading the special factor of the instruction cache in the test segment is taken by r/^^(icu hit/miss) Test mode. Figure 5 is a schematic diagram of the divergence chest test system. 21 1288242 [Main component symbol description] 500 digital logic test system 504 digital logic test device 508 test mode generator 512 data cache unit 502 integrated circuit chip 506 instruction classifier 510 instruction cache unit 514 memory management unit
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