JPH0342736A - Fault simulation method - Google Patents

Abstract

PURPOSE:To shorten calculation time by executing the logical simulation of a logic circuit by means of an input pattern, detecting signal lines which take only a specific logical value and previously removing a degenerate fault for the logical value of the signal line from the object of simulation. CONSTITUTION:Logical simultaion by the object test pattern of an object circuit is executed, and accordingly the signal lines (a)-(e) which take only the specific logical value is detected. For detecting the degenerate fault for the certain logical value X of the certain signal lines (a)-(e), it is necessary to input the test pattern making the signal lines (a)-(e) to the logical value which is not X. Consequently, the degenerate fault for the specific logical value cannot be detected in the signal lines (a)-(e) which take only the specific value. Thus, the fault which cannot be detected is removed from all the object faults as the fault for the undetection of a previous detection.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to failure simulation of logic circuits.

[Conventional technology]

Fault simulation is used to evaluate the quality of test patterns for testing logic circuits and to design test patterns.

This assumes a fault in which a signal line in a logic circuit degenerates to a specific logic value, and determines what percentage of such faults will be detected by a given input pattern and A simulation is used to determine which signal lines and which logic values are stuck-at faults that are not detected based on the pattern.

Fault simulation is useful in creating test patterns suitable for detecting defects in manufactured logic circuits.
Although it is extremely important, it generally takes a huge amount of calculation time and costs a lot of money to execute, even compared to logical simulations, etc., so a method to shorten the calculation time is desired. ing.

Most widely used, for example rVLS by Yukizo Kishita et al.
It is described on pages 249 to 254 of ``Design of I - Logic and Test'' published by Iwanami Shoten in 1985.

The simultaneous failure simulation method will be explained using FIG.

At step 1, which is the beginning of the simulation, all target faults are undetected faults.

Next, test patterns are input in order to perform a simulation.

In simulation 2 for one pattern, the targets are undetected faults that have not been detected by the input patterns so far, and the values observed at the output terminal of the logic circuit when those faults exist are determined. If the value differs from the value of a fault-free circuit, it is treated as a fault detected by that pattern and removed from the undetected faults in step 3.

In the method shown in FIG. 3, faults that are not detected until the end are evaluated using all input patterns, and a considerable portion of the total calculation time is spent on the evaluation.

Therefore, by removing in advance faults that are not detected until the end from the target faults, the overall calculation time can be shortened.

Conventionally, such faults to be eliminated in advance have been targeted at faults that cannot be detected by any input pattern due to the structure of the circuit, so-called redundant faults.

[Problem to be solved by the invention]

However, it is difficult to determine all redundant faults as described above from the circuit structure, and in reality, only those that can be easily discovered are targeted for advance deletion.

Furthermore, in general, failures that cannot be detected until the end are not only redundant failures, but are also often due to insufficient test patterns.

Therefore, although conventional methods are sufficiently effective in eliminating faults that cannot be detected until the end, they cannot cope with the speeding up of fault simulation.

[Means to solve the problem]

The fault simulation method of the present invention includes, in a fault simulation using an input pattern performed on a logic circuit, performing a logic simulation of the logic circuit using the input pattern and detecting a signal line that takes only a specific logic value; The configuration is such that the stuck-at fault of the signal line to the logical value is removed from the simulation target in advance.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a flowchart showing one embodiment of the present invention.

In step 11, logic simulation is first performed using the target test pattern of the target circuit.

As a result, signal lines that take only a specific logical value are detected.

In order to detect a stuck-at fault in a certain signal line to a certain logic value X, it is necessary to input a test pattern that causes the signal line to have a logic value other than X in a normal circuit without any faults.

Therefore, in a signal line that does not take the above-mentioned specific logic value, a stuck-at fault to that specific logic value cannot be detected.

For this reason, in step 12, such undetectable faults are removed from all target faults as previously discovered undetected faults.

After that, the same procedure as in the conventional example shown in 2.3 and Figure 3 is executed, and after completing all patterns, the pre-discovered undetected faults removed in step 12 are added to the undetected faults in step 13, and the final result is calculated. It is treated as an undetected failure.

Logic simulation is generally much faster than fault simulation.

Therefore, according to the method shown in Figure 1, by running one logical simulation at the same time, it is possible to eliminate in advance a portion of the undetected faults that consume much of the calculation time of the fault simulation, reducing the overall calculation time. Can be shortened.

A more specific circuit diagram used in the present invention will be explained with reference to FIG.

FIG. 2 is a circuit diagram of a logic circuit consisting of an OR gate 31 and an AND gate 32.

Input the test pattern to input terminals 33, 34 and 35,
The presence or absence of a failure is checked based on the signal value observed at the output terminal 36.

a, b, c, d, and e are signal lines.

For convenience of explanation, only two logical values, 0 and 1, are used, and a case will be considered in which there is only one stuck-at fault on the circuit.

Further, the stuck-at fault of the signal line ρ to the logical value V will be written as g/■.

Regarding the circuit in Figure 2, there are 5 signal lines, so 10 in total.
There may be several failures.

Among these, c/0, d/O, e/O and a/1, b/1. d/1 are equivalent faults that cannot be distinguished from each other, and the three are considered to be one set of faults.

Therefore, the target failures are alo and blo.

C/1. C/1. (clo, dlo, elo).

There are a total of six types of failures (C/1.b/1.d/1).

Consider inputting test patterns consisting of six patterns shown in Table 1 to the circuit shown in FIG.

C/1 according to the first pattern. C/1 becomes b/0, (c/O, d/0,
elo) is detected by the third pattern, and as a result of inputting all 6 patterns (C/1.b/1°d/
Only type T failures in 1) are undetected failures.

The present invention is applied to the circuit of FIG. 2 and the test pattern of Table 1.

The logic simulation in Table 1 shows that the signal line d takes only a logical value of 1, so the failure (C/1, b/1.d
/1) can be removed in advance.

As a result, evaluation of this failure for each of the six patterns can be omitted.

In this example, all other faults are detected using patterns 1 to 3, so there is no need to evaluate patterns 4 to 6, which significantly reduces calculation time. It is measured.

〔Effect of the invention〕

As described above, the present invention has the effect of significantly shortening calculation time by removing a portion of undetected faults in advance when performing fault simulation.

[Brief explanation of drawings]

1 and 2 are a flowchart and a circuit diagram for explaining an embodiment of the present invention, and FIG. 3 is a flowchart for explaining an example of a conventional failure simulation method. 1.2,3,11,12.13...procedure, 31...
・Or gate, 32...and gate, 33.343
5...Input terminal, 36...Output terminal.

Claims (1)

[Claims] In a fault simulation using an input pattern performed on a logic circuit, a logic simulation of the logic circuit is performed using the input pattern, a signal line that takes only a specific logic value is detected, and a signal line that takes only a specific logic value is detected. A fault simulation method characterized in that a stuck-at fault is removed from a simulation target in advance.