JPS60161571A - Failure simulation system - Google Patents

Abstract

PURPOSE:To effect a speedy failure simulation opeation of a logic circuit with a limited number of memories, by eliminating a gate remained intact on its condition by memorizing a condition of an anti-propagation gate of failure which failed propagation in the past. CONSTITUTION:For a condition of a gate failed to propagate caused by a failure 21 in the previous test, a pointer is planted in input pins 11, 13 of plant table 51 corresponding to the input pin and in entries 31, 32 corresponding to them respectively and for an entry 41 of failure responding planting table 61, a pointer in an input pin planting area 62 which plants the input pin 11 and in an area 62, a pointer of planting area 63 for the input pin 13 is planted. The anti-propagation which remained intact on its condition in accordance with this anti-propagation gate condition of failure is identified and eliminated from the object of failure propagation. Consequently, by checking only of propagation possibility of an input pin of a signal change gate, the failure propagation possibility in the following test can easily by made and a failure simulation of logical circuit can be done quickly with a reduced memory capacity without unnecessary trials.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a fault simulation method for logic circuits [Background of the Invention] In the conventional fault simulation method, the state of a circuit from a previous test is stored using a fault list. First method (parallel method, deductape method, concurrent method)
and the second method (S F
P: 5fnfle paultPropafati
on method).

The first method is applicable to both combinational circuits and sequential circuits, but the second method is applicable only to combinational circuits.

The first method uses a fault list to faithfully represent the fault propagation path at each simulation time.
A large area is required to store the fault list, and the fault list must be frequently added and deleted according to changes in the fault propagation state, resulting in an increase in processing time. be.

Further, in the second method, each test and each fault are processed independently, and the propagation path of each fault is not particularly stored, so a fault list is not required and the amount of memory required is small. However, since the fault propagation state in the previous test is unknown, for test patterns with few signal changes, unnecessary processing that overlaps with the previous test has to be performed, making it difficult to reduce processing time. The problem is that it can't be done.

[Purpose of the invention]

An object of the present invention is to provide a failure simulation method that eliminates the above problems and enables high-speed processing with a small amount of memory.

[Summary of the invention]

The number of faults detected in one test is small, about 2 to 3% of all faults, and only information regarding these detected faults is required as a simulation result. Therefore, if faults that are not detected by the test can be identified quickly, the number of faults to be processed can be reduced and the processing speed can be increased.

The identification method uses the fact that a non-propagable fault is undetectable, which is derived from the natural law that "fault manifestation and fault propagation are necessary and sufficient conditions for fault detection."

In order to determine the non-propagability of faults, we use a propagation blocking gate (propagation frontier) for faults that were non-propagable in the previous test.
Only the state of is memorized. As long as the state of this fault propagation blocking gate does not change, it is impossible for the fault to propagate beyond the propagation frontier, and the non-propagation can be easily checked.

In this way, non-propagable faults are identified at high speed and the number of trial faults is reduced, thereby shortening processing time.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is an explanatory diagram showing the state of fault propagation in a certain test pattern. 1 to 4 are AND gates, 5, 6
indicates the output edge pin.

21 is a hypothetical fault at the output pin of AND gate 1. In the test pattern, this fault 21 is connected to input pin 11 of AND gate 3, input pin 13 of AND gate 4.
However, by setting the logic values of input pins 12, 14, and 15 to 0'', the propagation to the output pin side is prevented. Therefore, the fault 21 does not propagate to the output edge pin 5.6, and this fault 21 is non-propagable.

Such propagation failures are stored using a table shown in FIG. The pointer storage table 51 corresponding to input pins has an entry corresponding to each input pin, and the pointer chains the failure number storage area.

For example, the entry 31 corresponding to the input pin 11 has a pointer pointing to the fault storage area 52 that stores the fault 21, and the entry 33 corresponding to the input pin 13 also points to the fault storage area 53 that stores the fault 21. A pointer is stored. In addition, a pointer storage table 61 for troubleshooting
is a pointer storage area having an entry for each failure, and this pointer chains the input pin number storage area.

For example, the entry 41 corresponding to the failure 21 stores a pointer pointing to the input pin storage area 62 that stores the input pin 11, and the input pin storage area 62 stores a manual bin storage area that stores the input pin 13. A pointer pointing to 63 is stored.

Next, a logical value storage table for checking the propagation possibility of input pins 11 to 15 will be explained.

FIG. 3 is an explanatory diagram showing a logical value storage table. 1
11 to 115 are entries for storing the logical values of the input pins 11 to 15 in the logical value storage table 100;
For example, '1' is stored in entry 111 as the logical value of input pin 11. Similarly, entries 112 to
115 has “0” as the logical value of input pins 12 to 15.
″.

111#, "0#, '0" are stored. The contents of each entry 111 to 115 of the logical value storage table 100 are updated as the input logical value changes.

Next, the present invention will be explained in detail with reference to the 70-chart in FIG. Each entry in the logical value storage table 100) IJ
Assume that when the signals 111 to 115 are in the above state, the logic value of the input pin 14 of the AND gate 4 changes from θ'' to '1'' in the next test pattern. At this time, the entry 114 of the logical value storage table 100 is updated from 101 to 11''.

First, input pin ii of the AND gate where the input signal has changed.
, ia (steps 210 and 220). Input pin 13 is unable to propagate as in the previous test, and the state of input pin 11 remains unchanged. Therefore, the propagation state of fault 21 has not changed as in the previous test, and this fault 21 does not pass through this test. However, it can be easily determined that it is undetectable.

Furthermore, assume that in the next test)-pattern, the logical value of mold/15 of the AND gate 4 changes from '0' to '1#. At this time, the entry 115 of the logical value storage table 100 is updated from 602 to 1". First, it is checked whether the input pin 13 has changed to the propagation enabled state (steps 210 and 220). The input pin 13 has changed to the propagation enabled state. Therefore, the fault 21 stored in the fault storage area 53 chained from the entry 33 of the table 51 is extracted as a propagation possibility fault.
1 is the target of propagation processing trials.

At this time, the propagation state regarding the fault 21 is removed from the pointer storage table 51 corresponding to the input pin and the pointer storage table 6e corresponding to the fault (step 230).

As explained above, you can easily check the possibility of fault propagation in the next test by simply checking the possibility of propagation of the input pin of the signal change gate based on the fault propagation state in the previous test. , it is possible to reduce unnecessary attempts at fault propagation processing and significantly speed up the process.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, most of the non-propagable faults can be easily identified, the number of trial faults can be significantly reduced, and the processing time of fault simulation can be reduced.

For example, in a circuit with 1000 gates and 900 failures, 1
The number of trial failures when applying 40 test patterns was 14 without using this method, but can be reduced to 3.5 using this method.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing an example of a fault propagation state, Fig. 2 is an explanatory diagram showing an example of a table structure and its contents for storing the propagation state, and Fig. 3 is an explanatory diagram showing a logical value storage table. 4 are flowcharts showing an example of the operation of the present invention. 1-4...AND gate, 5,6...Output edge pin, 11-15...Input pin, 21...Failure, 51
... Pointer storage table corresponding to input pins, 52.5
3...Fault storage area, 61...Failure response pointer storage table, 62.63...Input pin storage area. a 1 Zukan 32 Part 2 Figure 1 Procedural amendments, Showa 5th edition May Display of the case of the Commissioner of the Patent Office 1982 Patent application No. 151,640,000 Name of the invention Name of the person making the failure simulation method amendment (510) Nihon Co., Ltd. Hitachi Seisakusho Co., Ltd. Hitachi Seisakusho Co., Ltd. Tokyo 212-1111 (main representative) ``Detailed description of the invention'' column and drawings. Contents of the amendment ■: The scope of the claims will be amended as shown in the attached sheet. 2. The following amendments will be made to the detailed description of the invention. (1) 14 from “respectively” on page 4, line 13 of the specification
The lines up to "prevent" are corrected to "Since each is zr Orr, propagation to the output pin side is prevented." (2) Add ``This is a pointer storage area'' after ``Has'' on page 4, line 19 of the Meisho. (3) rl on page 6, line 15 of the specification box, 1. Delete J. (4) On page 7 of the specification letter, from the 11th line ``Tori'' to the 12th line ``Target.'' amended to ``Restore.'' (5) r230 on page 7, line 16 of the specification). ”, then
Add the following sentence. [In this way, propagation processing is performed on all restored faults with propagation potential, and it is checked whether the effect of the fault propagates to the output edge (steps 240, 250). If propagation is impossible, the state of the propagation blocking game 1- (propagation frontier) is registered in the table 51.61 (step 260). Since a propagable fault does not have a propagation blocking gate, it is unconditionally subject to a propagation trial in the primary test. j (6) Delete "<" on the 20th line of page 1 of the statement box. 3. Amend Figure 4 as shown in the attached drawing. The above appended claims (■) record the state of a propagation blocking gate of a fault that has become unpropagable in the past, identify a fault for which the state of the propagation blocking gate has not changed up to the present, and detect the fault; A fault simulation method that is characterized by determining that the fault propagation occurs and excluding the fault from being subject to fault propagation.

Claims (1)

[Claims] 1. Memorize the state of the propagation blocking gate of a fault that has become incapable of propagation in the past, identify the propagation blocking gate whose state has not changed until now, and identify the propagation blocking gate that has not changed. A fault simulation method characterized by excluding objects from fault propagation.