JPH01213724A - Testing method for electronic computer circuit - Google Patents

Abstract

PURPOSE:To reduce the number of objects where analysis of trouble positions is necessary by executing a test program to confirm the normal operation of a function circuit unit after confirming that all latch circuits are normal. CONSTITUTION:A test program 40 which executes the test of latch circuits is stored in a storage device 35 of a service processor system 32. A service processor 33 reads this test program 40, and an interface device (CCI) 34 issues a command according with contents of the command to an electronic computer system 30 to confirm that all latch circuits are normal. Thereafter, the service processor 33 executes the test program to confirm that electronic computer systems 31 and 31' are normally operated.

Description

[Detailed Description of the Invention] (Summary) To provide a method for testing an electronic computer circuit, which allows the electronic computer circuit to be tested in a short time and to easily identify a defective latch circuit. The test method for electronic computer circuits is to check the status of all latch circuits with a service processor, confirm that all latch circuits are normal, and then run the test program. to confirm that the functional circuit unit operates normally.

(Industrial Application Field) The present invention relates to a method for testing electronic computer circuits.

(Prior Art) Generally, before a computer is shipped, a test is conducted to confirm that the circuit of the computer functions normally. Conventional testing methods for such electronic computer circuits include the following. This involves running a test program on the computer's processor to check whether the various functions of the computer are working properly. This may be done not only by the computer's main processor, but also by the service processor.

A method for testing such an electronic computer circuit will be explained based on FIG. 3. In the figure, 1 is a computer system, 2
is a control unit of a central control unit (CPU), 3 is a main memory, 4 is a functional circuit unit of the CPU consisting of a combination of latch circuits such as adders and multipliers and gates G, and 4' is a similar multiplier. 4 is a functional circuit unit, 4 is another functional circuit unit, 5 is a service processor system, 6 is a service processor, 7 is an interface device (CCI) between the computer system 1 and the service processor system 5,
8 indicates a storage device of the service processor.

In an electronic computer having such a configuration, when a device is to be diagnosed, a test program group 9 is first prepared on the main storage device 3, and this test program group 9 is activated. Since the test program is composed of instructions that can be processed by the CPU, the test program is taken out one after another by the control circuit of the CPU, and processing operations are executed by each functional circuit unit of the CPU.

Here, the test program checks whether the CPU control circuit and each functional unit are functioning normally each time a plurality of instructions are executed by comparing the results with expected values prepared in advance. . That is, when the result does not match the expected value, it is determined that there is a failure in the CPU control device or the functional unit of the CPU.

Also, when a test is executed from the service processor system 5, the method is almost the same as above, and the test program group 10 on the storage device 8 of the service processor is taken out by the service processor 6 and sent to the control circuit 2 of the CPU via the CCl 7. The results are then executed by the functional units 4, 4'', 4'' of the CPU, and the results are compared with expected values to diagnose whether the circuit is operating normally.

(Problem to be Solved by the Invention) According to the conventional computer circuit testing method as described above, testing of each functional circuit unit requires executing a different program for each functional circuit unit. The problem is that it takes a lot of time. Furthermore, in order to identify which latch circuit in which functional circuit unit part of the computer is defective, these results must be further analyzed, which is very complicated.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for testing an electronic computer circuit that can test the electronic computer circuit in a short period of time and that can easily identify a defective latch circuit.

[Means to solve the problem]

Means for solving the above problems in the present invention is as shown in FIG. Then, it is confirmed 22 that all latch circuits are normal, and then a test program is executed 22 to confirm 23 that the functional circuit units operate normally.

(Function) In the present invention, since the states of all latch circuits of the electronic computer are tested first, defective latch circuits can be discovered at this stage. Therefore, it is possible to discover defects without depending on the subsequent execution of the test program, and therefore it is possible to efficiently test electronic computer circuits.

(Example) Hereinafter, an example of the method for testing an electronic computer circuit according to the present invention will be described based on the drawings.

FIG. 2 shows an embodiment of the method for testing an electronic computer circuit according to the present invention. The electronic computer system to which this embodiment is applied has a configuration as shown in FIG. In the same figure, 30 is an electronic computer system, 31.31' is a CPU functional circuit unit such as an adder/multiplier, and 3
2 is a service processor system, 33 is a service processor, 34 is an interface device (CCI) between the computer system and the service processor system, 35
indicates the storage device of the service processor. Also,
36 is a scan-in reset control circuit that generates a scan-in reset command to set the latch circuit of the CPU to the "0" or "1" state set at the time of design; 37;
38 is a scan-in control circuit that generates a scan-in command to invert the state of the latch circuit of the CPU from the state set at the time of design, and 38 is a scan-in control circuit that sequentially specifies addresses of the latch circuit that generates scan-in reset commands and scan-in commands. Address data register, 3
Reference numeral 9 indicates a scan-out control circuit that generates a scan-out command to read the state of the latch circuit of the CPU.

Here, the latch circuit in the computer circuit operates its state from the service processor system 32 by the functions of these control circuits 36 to 39 of an interface device (CCI) 34 located between the service processor 33 and the computer circuit. be able to. This operation is performed by a CCI command.

To test the latch circuit, a test program 40 for testing the latch circuit using this CCI command is stored in the storage device 35 of the service processor, and this test program 40 is transferred to the service processor 33.
reads the CCI command and sends it to the service processor 33.
issues the command to the CCl 34, and the CCl 34 issues a command to the computer system 30 according to the contents of the command.

This test program operates according to the flowchart shown in FIG.

That is, first, the scan address data register 38 is set to an initial value (S1), and a scan-in reset is applied to the latch circuit at that address (S2). Then, scan out the latch circuit at this address, and this output will be A.
(S3). This operation is executed for the latch circuits of all addresses54) (S5), and when the output of all addresses is stored in A, it is compared with the expected value prepared in advance (S6) (S7). If so, the address of this latch circuit is recorded (S8). If the outputs of the latch circuits at all addresses match the expected values, scan-in is performed on the latch circuits at all addresses (S9) to (313) in the same way as in the case described above. The outputs of the latch circuits of all the addresses recorded in are compared with the expected values (S14) (S15), and if they do not match, the address of the defective latch circuit is recorded (S16). If the outputs and expected values match in all address circuits, records A and B are compared (S17) (318). If these values are normal, they do not match at each address, so if there are several addresses, record the addresses (S19), and if they do not match at all addresses, write all the latches of the computer. Assuming that the circuit is normal (S20), the test regarding this latch circuit ends.

At this stage, in a device with a latch circuit failure, the address at which the failure has occurred is recorded, so by outputting and referring to this record, it is possible to easily take measures such as repair. Further, this test regarding latch circuits can be completed in a few seconds even when the number of latch circuits is about 100,000, for example, and can be executed in a relatively short time.

In this embodiment, a circuit test using a conventional test program is performed only on devices that pass the latch circuit test. Since the details of this test are the same as those described previously, detailed explanation thereof will be omitted.

Therefore, according to the method for testing computer circuits according to the present embodiment, if an electronic computer has a latch circuit failure, the address of the latch with the failure can be known by testing the latch circuit in advance, so that measures can be taken quickly. can do.

Furthermore, since the electronic computer that executes the next test program has no failures at least with respect to the latch circuit, circuits with fewer failures and low failure rates are tested. Therefore, the number of targets that need to be analyzed for faulty parts due to circuit defects is reduced, and the overall time required for testing can be shortened. Furthermore, if the fault is related to a latch circuit, the address of the fault can be accurately determined in a short time by testing the latch circuit at the previous stage, and countermeasures can be taken quickly.

In the above embodiment, the output of the latch circuit is once stored for all addresses and compared with the expected value, but instead of storing the output of all the latch circuits. , each time the output is obtained, it may be compared with the expected value of that address. Furthermore, the test can be carried out by simply performing an exclusive OR of the scan-in reset output and the scan-in output of the latch circuit at the same address and confirming that the value becomes "1". . In this case, there is no need to store the above-mentioned expected value, and the storage device of the service processor can be used for other purposes.

(Effects of the Invention) As explained above, according to the present invention, a method for testing an electronic computer circuit is such that a service processor checks the status of all latch circuits to confirm that all latch circuits are normal. After that, a test program is run to confirm that the functional circuit unit operates normally, so if a computer has a latch circuit failure, a latch circuit test is performed in advance to accurately identify the latch with the failure. Knowing this allows you to take prompt action. Furthermore, since the electronic computer that executes the next test program has no failures at least with respect to the latch circuit, circuits with fewer failures and low failure rates are tested. Therefore, the number of targets that need to be analyzed for faulty parts due to circuit defects is reduced, and the overall time required for testing can be shortened.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing the state of a latch test in an embodiment of the computer circuit testing method according to the invention, and Fig. 3 is a diagram showing the computer circuit testing method using a test program. FIG. 4 is a flowchart showing a test method for the latch shown in FIG. 2. ζj6 day moon principle itz Figure 1 Figure 4 ■

Claims (1)

[Claims] In an electronic computer circuit testing method for testing the state of an electronic computer circuit, a service processor checks the states of all latch circuits (
21), confirm that all latch circuits are normal (22), then run a test program (22), and confirm that the functional circuit units operate normally (23). Test method for electronic computer circuits.