JPS62154035A - System developing supporting device - Google Patents

Abstract

PURPOSE:To designate various developing supporting function modes by retrieving an associative memory with the executing memory address during the execution of a programs and reading the corresponding system developing supporting function mode. CONSTITUTION:In an associative memory 10, one pair or plural pairs of the memory address and the 'system developing supporting function' mode at the memory address are written by the associative memory writing signal. At the time of the execution of the program, the memory address of the associative memory 10 is retrieved by the real time, when the memory address coincident with the programs executing memory address exists at the time of the writing or reading of a memory 2, an interrupting signal is outputted from a signal generating part 11 to a CPU 1, simultaneously, the corresponding 'system developing supporting function' mode is set to a mode register 12, by the mode reading signal from the CPU 1, a gate 13 is opened and the mode data are outputted to the CPU 1.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides system development support that can provide development support in various modes by interrupting CPtJ while a CPU is executing a program. Regarding equipment.

[Technical background of the invention and its problems] In this type of system development support device, when you want to stop a program executed by a CPU, you can
The stop memory address was stored in a register in advance, and compared with the memory address currently being executed, an interrupt was generated.

In this case, since only one program stop memory address to be stopped could be set, it was not possible to stop at multiple memory addresses.

Furthermore, since it could only perform the program stop function when supporting system development, it was not possible to display the contents of registers or generate test signals without stopping program execution.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a system development support device capable of specifying various development support function modes even for a plurality of program memory addresses. This is the purpose.

[Summary of the Invention 1] A summary of the present invention for achieving the above object is to provide a system development support device that interrupts the CPU and executes a system development support function mode while the CPU is executing a program. An associative memory is provided in which the system development support function mode is stored in advance in association with the system development support function mode, and when the associative memory is searched at the execution memory address during execution of the program and a memory address matching the execution memory address is found, The present invention is characterized in that it is configured to output an interrupt signal to the CPtJ and read out the system development support function mode corresponding to the memory address.

[Embodiment 1 of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the main configuration of the device according to the present invention;
FIG. 2 is a block diagram of the apparatus of this embodiment.

First, the overall configuration of the embodiment apparatus will be explained with reference to FIG. 2. In the figure, a CPU 1 is in charge of controlling the apparatus of this embodiment, and is designed to execute and control the operations of the various apparatuses described below in accordance with a predetermined program. The memory 2 is for storing various data, and the keyboard 3 is for inputting information based on operations by the developer.

Further, the CRT 4 displays various information under the control of the CPU 1. Reference numeral 5 denotes a system development support section, which interrupts the CPUI at a predetermined program memory address to provide development support in various modes.

Next, the specific configuration of the system development support section 5 will be explained with reference to FIG.

This system development support section 5 includes an associative memory 10° signal generation section 11. mode register] 2 and a gate 13.

The associative memory 10 is a content addressable memory that stores data corresponding to various contents, and outputs the data corresponding to the contents when the same contents as the above contents are input. . In the case of the tree embodiment, the system development support function mode to be performed at the memory address is stored in advance in correspondence with the memory address.

For this purpose, the associative memory 10 includes the keyboard 3
Data (memory address data, mode data) input from the CPU 1 is stored based on an associative memory write command from the CPU 1.

Then, while the program is running, the program memory address is input in real time, and if the same memory address as a pre-stored memory address is input, the memory address presence signal and the mode data corresponding to that memory address are transmitted. It is designed to be output.

The signal generating unit 11 inputs a memory existence signal from the associative memory 10 and outputs an interrupt signal to the CPU 1 when the CPU 1 is outputting a memory write/read signal for driving and controlling the memory 2. It is something to do. Also, at this timing, the mode register 1
A register set signal is output for 2.

The mode register 12 sets the mode data read from the associative memory 10 based on the input of the register set signal.

The gate 13 is provided between the mode register 12 and the data line, and is connected to the CPU inputting the interrupt signal.
The gate is opened based on the mode read signal outputted by the mode register 12, and the contents of the mode register 12 are transferred to the data line.

The operation of the device configured as above will be explained.

The associative memory 10 has in advance one or more sets of memory addresses and a "system development support function" at that memory address.
Write the mode using the associative memo 1 write signal.

Then, when the program is executed, the memory address of the associative memory 10 is searched in real time, and if a memory address that matches the program execution memory address exists when writing or reading from the memory 2, an interrupt signal is sent from the signal generator 1 to the CPU 1. At the same time, set the corresponding "system development support function" mode in the mode register 12, and
The gate 13 is opened by the mode read signal from the PU1 and the mode data is outputted to the CPU1.

Therefore, if the mode data is a stop command, C
Program execution of PU1 can be stopped. Moreover, since the associative memory 10 can store stop modes at a plurality of memory addresses, it is extremely functional in supporting system development.

Furthermore, according to the present embodiment, the system development support function mode is not limited to the stop mode, so that various modes effective for development support can be performed during program execution. For example, it is possible to execute a mode in which program execution is stopped and the contents of the register group at that time are displayed on the CRT 4. It is also possible to operate a mode in which when a certain memory address is reached, the contents of the register group corresponding to that memory address are displayed on the CRT 4 without stopping the execution of the program. In addition, a mode may be used in which a test signal is output when a certain memory address is reached.

In this way, in the device of this embodiment, various "system development support function" modes can be designated at a plurality of memory addresses during program execution, and various modes can be easily designated.

Note that the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the gist of the present invention.

[Effects of the Invention] As explained above, according to the present invention, various "system development support function" modes can be easily specified using one or more sets of memory addresses during program execution, and Since it is not complicated, it is possible to provide an inexpensive system development support device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the waist part of the embodiment device according to the present invention;
FIG. 2 is a block diagram of the apparatus of this embodiment. 1...CPU, 3...Input section, 4...Display section, 1
0... Content addressable memory, 11... Signal generation unit, 12...
-Mode register, 13...gate.

Claims (1)

[Claims] A system development support device that interrupts a CPU to execute a system development support function mode while the CPU is executing a program, comprising an associative memory in which the system development support function mode is stored in advance in association with a memory address. , searches the associative memory for the execution memory address during program execution, and outputs an interrupt signal to the CPU when a memory address that matches the execution memory address exists; A system development support device characterized by being configured to read a system development support function mode.