JPS5952349A - Instruction pre-fetch controller - Google Patents

Abstract

PURPOSE:To improve the information processing performance, by storing previously an instruction of a branching receiver of a conditional branch instruction into a prescribed buffer and reducing the memory accesses furing the branching as well as the prefetching frequencies of instructions. CONSTITUTION:An instruction is usually stored into an instruction pre-fetch buffer 2 from an address designated by a pre-fetch instruction address register 9. In this case, a storage start instruction detector 1 checks an instruction which is pre-fetched and then activates a storage instruction detecting signal 6 when a storage start instruction is detected. After the signal 6 becomes active, the subsequent instructions are stored not only in the buffer 2 but in an instruction storage buffer 5. A multiplexer 3 usually extracts an instruction out of the buffer 2, but extract it out of the buffer 5 when a branch signal 7 is active. This signal 7 becomes active in case a conditional branch instruction s executed and branched within an operator 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction prefetch control device, and particularly to a control method for instruction prefetch in an information processing device.

Generally, a processor of an information processing device executes a program by repeating the following four steps (the second and third steps may be omitted depending on the instruction).

First step: retrieve the next instruction from memory.

Second step; read the operand.

Third step: Execute the instruction.

Fourth step; write the results.

Furthermore, there are the following two methods for executing the conventional information processing apparatus. The first method executes these steps serially, and the second method retrieves more consecutive instructions from memory and stores them in a prefetch-only internal random φ access memory (RAM) called instruction buffered. This is then executed sequentially.

In the first method, the next instruction is fetched from memory when the currently executing instruction is completely finished, whereas in the second method, the next instruction is fetched while the previous instruction is being executed. Since the next instruction can be executed immediately after the previous instruction finishes executing, the time required to fetch the instruction can be significantly reduced.

However, even in the second method, in the case of a branch instruction that changes the flow of instructions, all instructions in the prefetch buffer that have been prefetched must be invalidated and a new instruction must be fetched from the branch destination address. Must be.

Further, in the case of a conditional branch instruction, in which whether to branch or not is determined depending on the execution result of the instruction, preemption control becomes particularly difficult.

In order to overcome the above-mentioned drawbacks, in the conventional technology, there is a method for effectively dealing with prefetching by providing two or more instruction buffers for prefetching instructions, their control circuits, and branch instruction detection circuits. It is considered. In other words, when an instruction is prefetched, it is detected whether the instruction is a branch instruction or not, and if it is an unconditional branch instruction, the branch destination address is calculated and prefetch is continued from that address, and if it is a conditional branch instruction, the branch is executed. Taking into account both success and failure cases, prefetching from the branch destination address and not branching (
- Perform case prefetching in parallel to two instruction buffers.

Therefore, when actually executing a conditional branch instruction, one of the two instruction buffers is selected depending on whether the branch is successful or unsuccessful, and subsequent execution is performed from that buffer.

This method is often used in large computers that require high-speed processing, along with the so-called pipeline control method that processes multiple instructions at the same time. takes both cases into consideration when fetching instructions, so store the instructions (・
This has the disadvantage that the number of accesses to the main memory increases, which reduces the efficiency of main memory use.

An object of the present invention is to provide an instruction preemption control device that solves the above-mentioned drawbacks.

In addition to the instruction prefetch buffer, the present invention also includes an instruction storage buffer, an instruction (storage start instruction) means for instructing the instruction storage buffer to start storing, a detector for detecting this instruction when the instruction is prefetched, and a detector for detecting this instruction when the instruction is prefetched. conditional branch instruction means for specifying an instruction storage buffer as a branch destination, and when the storage start instruction is detected during instruction prefetching, subsequent prefetching instructions are transferred by the size of the instruction storage buffer, not only to the instruction prefetching rebuffer, but also to the instruction prefetching rebuffer. The instruction prefetch control device is characterized in that it is configured to also store instructions in an instruction storage buffer, and to take out instructions from the instruction storage buffer when branching by the conditional branch instruction.

According to the present invention, information processing performance is improved by storing a branch destination instruction of a conditional branch instruction in a predetermined buffer, reducing memory access at the time of branching, and reducing the number of instruction prefetching. 4. Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an outline of an instruction preemption control device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a program using the instruction preemption control device of FIG. 1, and FIG.
The figure is an explanatory diagram showing the contents of the buffer during program execution.

In FIG. 1, this instruction prefetch control device includes a storage start instruction detector 1 that outputs a storage instruction detection signal 6, an instruction prefetch buffer 2, a multiplexer 3, an arithmetic unit 4 that outputs a branch signal 7, and a storage start instruction detector 1 that outputs a storage instruction detection signal 6. Storage buffer 5, program counter save register 8, and prefetch instruction address register 9
and a program counter 10. Normally, instructions are stored in the instruction prefetch buffer 2 starting from the address specified by the prefetch instruction address register 9.

At this time, the storage start command detector 1 checks the instruction to be prefetched, and makes the storage command detection signal 6 active if it is a storage start command. When this signal 6 becomes active, it not only stores subsequent instructions in the instruction prefetch buffer 2, but also stores subsequent instructions in the instruction prefetch buffer 2.
It is also stored in the instruction storage buffer 5. However, the size is the size of the instruction storage buffer 5. multiplexer 3
The command 6 separates the fetching of instructions from the prefetch buffer 2 and the instruction storage buffer 5. Normally, the instruction is taken out from the instruction prefetch buffer 2, but when the branch signal 7 becomes active, the instruction is taken out from the instruction storage buffer 5. The branch signal 7 becomes active in the arithmetic unit 4 when a conditional branch instruction is executed and a branch is taken. While the instruction is also fetched from the instruction storage buffer 5 (・), the instruction following the instruction stored in the instruction storage buffer 5 is prefetched in the instruction prefetch buffer 2, and after all the contents of the instruction storage buffer 5 are fetched, the prefetched instruction continues to be read. Extract from buffer 2. For this reason,
When a storage start instruction is detected, the contents of the prefetch instruction address register 9 are saved in the program counter save register 8, and when the branch signal 7 becomes active, this value is returned to the program counter 10. A value obtained by adding the size of the instruction storage buffer 5 to the value of the program counter 10 is set in the prefetching instruction address register 9, and the prefetching of the instruction prefetching buffer 2 is performed again.

Next, an example of the operation of the present invention will be described using the explanatory diagram of the program example in FIG. 2 and the explanatory diagram showing the transition of the contents of the buffer in FIG. is the storage start command (S
AVE), and 16 is a conditional branch instruction (JC). 11, 13, 14, 15.17 is program (2),
a, a, a, @. First of all, program (A)
11 enters the instruction prefetch buffer 2 and is executed (15tep in FIG. 3).

When (SAVE) 12 is prefetched, it is detected by the detector 1 (2 steps), and the program (E13) is stored in both the instruction prefetch buffer 2 and the instruction storage buffer 50 (3 steps). ),
14 and 15 are taken out from instruction prefetch buffer 2 (4
, 5 steps), and the JC is executed (37).

At this time, if the branch is established, program 013 is taken out from the instruction storage buffer 5 (6°7 steps
). At this time, the program 014 is stored in the instruction prefetch buffer 2.
Preemption begins (8 steps).

When the execution of the program 813 in the instruction storage buffer 5 is finished, the fetching of instructions from the instruction prefetch buffer 2 starts, and the programs (Q, (I), 14, 15 are executed (9)
．． 10 steps). Next, the JC instruction 38 is executed, and if the branch is not taken, the program @17 in the instruction prefetch buffer 2 is executed as is.

As described above, according to the present invention, the instruction at the branch destination is stored in the instruction storage buffer in advance, so memory access at the time of branching is no longer necessary, and while the instruction in the instruction storage buffer is being executed, instruction prefetching is performed. Since instructions subsequent to the instruction storage buffer can be prefetched in parallel, information processing performance can be significantly improved.

In this embodiment, an example is shown in which one instruction storage buffer is used, but by using a plurality of instruction buffers, it is also possible to execute a nested loop program at high speed.

In addition, in FIG. 3, the contents of the instruction prefetch buffer 18.1
9, 20, 21, 25.26 and the contents of the instruction storage buffer 31.32 indicate the buffer in which the instruction is being accepted.

[Brief explanation of the drawing]

9- Fig. 1 is a block diagram showing an outline of an instruction preemption control device according to an embodiment of the present invention, Fig. 2 is an explanatory diagram showing an example of a program using the embodiment of the present invention, and Fig. 3 is a block diagram showing an outline of an instruction preemption control device according to an embodiment of the present invention. It is an explanatory diagram showing transition of re-buffering when using an example. In the internal causes, 1...Storage start instruction detector, 2...Instruction prefetch buffer, 3...Multiplexer, 4...
... Arithmetic unit, 5 ... Instruction storage buffer,
6... Store instruction detection signal, 7... Branch signal, 8... Program counter save register, 9... Preemption instruction address register, 10...
...Program counter, 11...Program prisoner, 12...Storage start command (SAVE)
, 13...Program example, 14...Program 0.15...Program 0.16...
...Conditional branch instruction (JC), 17...Program 0.18 to 26...Contents of instruction prefetch buffer, 27 to 35...Instruction storage buffer Contents, 36... Execution of storage start command, 37゜Figure 2 Figure 3

Claims (1)

[Claims] An instruction preemption control device configured to read an execution instruction in advance from a storage means and store it in an instruction prefetch buffer, comprising: an instruction storage buffer; and a storage start command means for specifying that a prefetch instruction is stored in the instruction storage buffer; , comprising: a detector for detecting the storage start instruction; and a conditional branch instruction means for specifying the instruction storage buffer as a branch destination; The instructions are stored in a buffer and the instruction storage buffer, and when the conditional branch instruction is executed and a branch is taken due to the satisfaction of a condition, the execution instruction is retrieved from the instruction storage buffer (
- An instruction preemption control device f.