JPH0527972A - Instruction prefetch device - Google Patents

Abstract

PURPOSE:To suppress memory access for prefetching an instruction at an irreducibly minimum and to facilitate access to data in the same memory. CONSTITUTION:Each time an instruction read signal 7 is impressed from a read signal generator 6 to a memory 1, two instructions in the memory 1 starting from an address designated through an address line 5 by an address generator 1 is read through a fetch line 2. Each time an instruction output signal 8 is impressed, an instruction fetch queue 3 successively supplies read instructions to a processor as an output instruction 11 one by one from the small address and between this instruction fetch queue 3 and the memory 1, a jump instruction detection part 9 is interposed. When a branching instruction is contained in the instructions read by the instruction fetch queue 3, a jump instruction detecting signal 10 is outputted from a jump instruction detection part 9 to the read signal generator 6 so as to temporarily stop the read of the instructions from the memory 1 until the branch destination address of the branching instruction is fixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction prefetch device for preliminarily reading an instruction from a memory before decoding and executing the instruction by a processor.

[0002]

2. Description of the Related Art Recent processors have been improved in performance so that the instructions constituting a program can be read out from a memory at high speed. However, since the memory is used not only for storing instructions to be decoded / executed by the processor but also for storing data that is not the target of decoding / execution, if the instruction read frequency increases The frequency of waiting for data access to the memory is relatively high. Therefore, an instruction prefetch device is indispensable in such a manner that a plurality of instructions are simultaneously read out by one access from a memory and prefetching of the instructions is advanced, while the prefetched plurality of instructions are supplied to the processor one instruction at a time. ..

FIG. 3 is a block diagram showing the configuration of a conventional instruction prefetch device. Reference numeral 1 in the figure is a memory in which instructions and data are stored, and two instructions can be read simultaneously through the fetch line 2. Reference numeral 3 is an instruction fetch queue having an instruction storage area for 5 instructions. When a free area of 2 instructions or more is made available, the next 2 instructions are read from the memory 1 while the already read instruction is output as an instruction output signal. Each time 8 is given, one instruction is sequentially supplied to the processor as an output instruction 11 in ascending order of address. Reference numeral 4 is an address generator for sequentially designating the address of the instruction to be prefetched next from the memory 1 through the address line 5.
Outputs an instruction read signal 7 for giving the read timing of the instruction of two consecutive addresses starting from the address designated by the address generator 4.
Is a read signal generator that sequentially outputs to.

The operation of the conventional instruction prefetch device configured as described above will be sequentially described with reference to the timing chart shown in FIG. However, in the initial state, all the instruction storage areas of the instruction fetch queue 3 are empty, and the address on the address line 5 starts from n. Further, both the command read signal 7 and the command output signal 8 are L.
Assume active during OW.

First, while the address generator 4 indicates the address n to the memory 1 through the address line 5, the read signal generator 6 sets the instruction read signal 7 to the memory 1 to LOW. Then, two instructions (n, n + 1) are read from the memory 1 through the fetch line 2, and these two instructions are simultaneously read into the instruction fetch queue 3. After that, when the instruction output signal 8 becomes LOW, one instruction (n) having the smallest address among the two prefetched instructions is supplied from the instruction fetch queue 3 to the processor as the output instruction 11.

At the time when the instruction (n) is supplied to the processor as the output instruction 11, the instruction fetch queue 3 has an empty area for four instructions, so that the next two instructions can be prefetched, and the read signal generator 6 is The instruction read signal 7 can be made LOW again. That is, when the instruction read signal 7 becomes LOW, the address line 5
The upper address is updated to n + 2, and the next two instructions (n + 2, n + 3) from the memory 1 are fetched from the instruction fetch queue 3
Prefetched to. And the command output signal 8 is LO
When it reaches W, one instruction (n + 1) with the smallest address among the remaining prefetched instructions is supplied from the instruction fetch queue 3 to the processor as the output instruction 11.

When the instruction (n + 1) is supplied to the processor as the output instruction 11, the instruction fetch queue 3 has 3
Since there is an empty area for instructions, the next two instructions can be prefetched, and the read signal generator 6 can set the instruction read signal 7 to LOW again. That is,
When the instruction read signal 7 becomes LOW, the address on the address line 5 has been updated to n + 4.
The next two instructions (n + 4, n + 5) are prefetched into the instruction fetch queue 3 in the same manner. However, in the example shown in FIG. 4, the instruction output signal 8 is temporarily kept HIGH, and the instruction fetch queue 3 does not immediately supply the instruction to the processor. Moreover, the two instructions (n + 4, n + 5)
Instruction fetch queue 3 when prefetched up to
Since there is only one instruction free area in the address line 5,
Even though the upper address is updated to n + 6, the instruction prefetch from the memory 1 based on the address is not performed. When the instruction output signal 8 becomes LOW next as time elapses, one instruction (n + 2) with the smallest address among the remaining prefetched instructions.
Is output from the instruction fetch queue 3 as an output instruction 11.

When the instruction (n + 2) is supplied from the instruction fetch queue 3 to the processor as the output instruction 11 in this way, an empty area for two instructions is created in the instruction fetch queue 3 and the next instruction read signal 7 is issued. Based on the address n + 6 on the address line 5 which has already been updated when it becomes LOW, the next two instructions (n + 6, n
+7) is prefetched to the instruction fetch queue 3.

After this, every time the instruction output signal 8 becomes LOW twice and two instructions are output from the instruction fetch queue 3, the instruction read signal 7 becomes LOW once and the instruction fetch queue 3 becomes 2 times. Instructions will be prefetched.

As described above, according to the present instruction prefetch device, since two instructions are simultaneously prefetched from the memory 1, the memory access frequency for instruction fetch is reduced as compared with the case where the processor fetches one instruction at a time.
Data access to the memory 1 becomes relatively easy.

[0011]

The above-described conventional instruction prefetch device prefetches two instructions one after another regardless of the type of instruction as long as the instruction fetch queue 3 has a free space of two instructions or more. Because of the configuration, the instruction fetch queue 3 reads an instruction that causes a jump to an address such as an unconditional jump instruction, an unconditional call instruction of a subroutine, and an unconditional return instruction, that is, an unconditional branch instruction, a conditional jump instruction, and a subroutine. Even if an instruction such as a conditional call instruction or a conditional return instruction that may cause a jump to the address, that is, a conditional branch instruction is read, another instruction stored in the subsequent address of the instruction in the memory 1 It was prefetched one after another.

When an unconditional branch instruction of the above branch instructions is prefetched, the execution of the program is always skipped to the branch destination after the processor decodes the unconditional branch instruction. The prefetch of the instruction is wasted and unnecessary memory access is executed for the instruction fetch. Even if a conditional branch instruction is prefetched, the execution of the program may jump to the branch destination after the processor decodes the conditional branch instruction. Therefore, the prefetch of the instruction at the subsequent address performed before the decoding is useless. Similarly, unnecessary memory access is executed for instruction fetch.

When unnecessary memory accesses are successively performed for instruction fetching in this manner, not only the data access is delayed by that amount, but also the unnecessary memory accesses are applied to the access prohibited area. In this case, an interrupt occurs and the processor has to perform unnecessary processing, which causes a problem that the instruction execution performance of the processor deteriorates.

An object of the present invention is to provide an instruction prefetch device for supplying a plurality of prefetched instructions to the processor one by one while advancing the instruction prefetch in such a manner that a plurality of instructions are simultaneously read from a memory by one access. The purpose is to minimize memory access for prefetching instructions.

[0015]

In order to solve the above problems, the present invention has a configuration in which, when an instruction fetch queue prefetches a branch instruction, the prefetch is suspended until the branch destination address of the branch instruction is determined. It was adopted.

More specifically, according to the present invention, an address generator for sequentially designating an address of an instruction to be prefetched next from a memory, and a plurality of consecutive address instructions starting from the address designated by the address generator. Read signal generator for sequentially outputting instruction read signals for giving read timings to the memory and a plurality of instructions read simultaneously from the memory each time the instruction read signal is given to the memory 1 in ascending order of address
Whether an instruction fetch queue for sequentially supplying instructions to the processor and a plurality of instructions read by the instruction fetch queue include a branch instruction that causes a jump in an address or a branch instruction that may cause a jump in an address If a branch instruction is detected by sequentially checking whether any branch instruction is included, the jump instruction detecting unit that temporarily stops the output of the instruction read signal by the read signal generator until the branch destination address of the branch instruction is determined. It adopts a configuration with and.

[0017]

According to the present invention described above, while the address generator and the read signal generator work in the same manner as in the prior art, the instructions are read into the instruction fetch queue in such a manner that a plurality of instructions are simultaneously read from the memory with one access. Then, the plurality of read instructions are sequentially supplied to the processor one instruction at a time from the instruction fetch queue in ascending order of address. Therefore, the frequency of memory access for prefetch is reduced, and data access to the memory is facilitated.

However, the jump instruction detection unit includes a branch instruction that causes a jump in an address, that is, an unconditional branch instruction, and a branch instruction that may cause a jump in an instruction, that is, a conditional branch instruction, in the instructions read by the instruction fetch queue. Is always inspected. If any of the branch instructions is included, the branch destination address of the branch instruction determined to be included by the inspection is determined. Since the output of the instruction read signal by the read signal generator is temporarily stopped, the reading of the instruction into the instruction fetch queue is interrupted. Therefore, prefetching of the instruction at the subsequent address of the branch instruction is suppressed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an instruction prefetch device according to an embodiment of the present invention. The memory 1, the instruction fetch queue 3, the address generator 4, and the read signal generator 6 in the figure each have the same configuration as the conventional one, and therefore detailed description thereof will be omitted. The present embodiment is different from the conventional one in that the jump instruction detecting unit 9 is interposed between the memory 1 and the instruction fetch queue 3. All the instructions read from the memory 1 are read into the instruction fetch queue 3 through the jump instruction detection unit 9, and the jump instruction detection unit 9 causes a jump in an address in the instructions read by the instruction fetch queue 3. An unconditional branch instruction or a conditional branch instruction that may cause a jump in the address is sequentially checked, and if any branch instruction is detected, the branch of the branch instruction is detected. The skip command detection signal 10 is output so that the output of the command read signal 7 from the read signal generator 6 is temporarily stopped until the destination address is fixed. The read signal generator 6 operates only when the jump instruction detection signal 10 is inactive and outputs the instruction read signal 7.

The operation of the instruction prefetch device of this embodiment having the above configuration will be sequentially described with reference to the timing chart shown in FIG. However, in the initial state, all the instruction storage areas of the instruction fetch queue 3 are empty, and the address on the address line 5 starts from n.
The command read signal 7, the command output signal 8 and the jump command detection signal 10 are all active when LOW. Further, it is assumed that an unconditional branch instruction is stored in the address n + 4 of the memory 1 and an instruction other than the branch instruction is stored in another address of the memory 1.

First, the read signal generator 6 sets the instruction read signal 7 to the memory 1 to LOW while the address generator 4 indicates the address n to the memory 1 through the address line 5. Then, two instructions (n, n + 1) are read from the memory 1 through the fetch line 2, and these two instructions are simultaneously read into the instruction fetch queue 3 through the jump instruction detecting unit 9. Since none of these two instructions is a branch instruction, the jump instruction detection signal 1
0 maintains HIGH. After this, the command output signal 8 is L
At the time of reaching OW, one instruction (n) having the smallest address among the two prefetched instructions is supplied from the instruction fetch queue 3 to the processor as the output instruction 11.

At the time when the instruction (n) is supplied to the processor as the output instruction 11, the instruction fetch queue 3 has an empty area for four instructions, so that the next two instructions can be prefetched, and the read signal generator 6 The instruction read signal 7 can be made LOW again. That is, when the instruction read signal 7 becomes LOW, the address line 5
The upper address is updated to n + 2, and the next two instructions (n + 2, n + 3) from the memory 1 are prefetched to the instruction fetch queue 3 through the jump instruction detection unit 9. However, since these two instructions are not branch instructions as well, the jump instruction detection signal 10 does not become LOW. Then, when the instruction output signal 8 becomes LOW, one instruction (n +) with the smallest address among the remaining prefetched instructions (n +
1) is supplied from the instruction fetch queue 3 to the processor as the output instruction 11.

When the instruction (n + 1) is supplied to the processor as the output instruction 11, 3 is stored in the instruction fetch queue 3.
Since there is an empty area for instructions, the next two instructions can be prefetched, and the read signal generator 6 can set the instruction read signal 7 to LOW again. That is,
When the instruction read signal 7 becomes LOW, the address on the address line 5 has been updated to n + 4.
From the next two instructions (n + 4, n + 5) are skipped
Is prefetched to the instruction fetch queue 3 in the same manner. However, since the instruction at address n + 4 is an unconditional branch instruction, the jump instruction detection unit 9 sets the jump instruction detection signal 10 to LOW for the read signal generator 6. In this case, only one instruction empty area remains in the instruction fetch queue 3, but while the read signal generator 6 receives the skip instruction detection signal 10 at the LOW level, the instruction fetch queue 3 temporarily stores two instructions. Even when the empty area can be secured, the read signal generator 6 does not set the instruction read signal 7 to the memory 1 to LOW, and the address generator 5 maintains the updated address n + 6 on the address line 5.

In the example shown in FIG. 2, since the instruction output signal 8 temporarily maintains HIGH at this point, the instruction fetch queue 3 does not immediately supply an instruction to the processor. When the instruction output signal 8 becomes LOW, one instruction (n + 2) with the smallest address among the remaining prefetched instructions is output from the instruction fetch queue 3 as the output instruction 11. In this way, when the instruction (n + 2) is supplied from the instruction fetch queue 3 to the processor as the output instruction 11, the instruction fetch queue 3 has a free space for two instructions. However, even if a space for two instructions is created in the instruction fetch queue 3 in this way, as described above, the read signal generator 6
Is receiving the LOW level jump instruction detection signal 10, the read signal generator 6 is different from the conventional one in the memory 1.
In response to this, the instruction read signal 7 is held HIGH. Therefore, the following two instructions (n + 6, n +
7) is not read into the instruction fetch queue 3 and unnecessary memory access for prefetch is avoided.

However, as described above, the instruction fetch queue 3
Even while the reading of the instruction to the processor is suspended, the supply of the remaining instructions prefetched to the instruction fetch queue 3 to the processor is continued. That is, every time the instruction output signal 8 becomes LOW, the instruction (n + 3) and the instruction (n +
4) are sequentially supplied to the processor from the instruction fetch queue 3 as output instructions 11 one by one.
When the instruction (n + 4), which is a branch instruction, is decoded by the processor, the branch destination address (here, address m) of the branch instruction is determined. When the branch destination address m is determined in this way, the jump instruction detection signal 10
Are returned to HIGH, and the address generator 4 indicates the branch destination address m to the memory 1 through the address line 5. Then, the jump instruction detection signal 10 as the input signal
The read signal generator 6, which has been returned to HIGH,
The output of the instruction read signal 7 is restarted.

Thus, when the read signal generator 6 sets the instruction read signal 7 to LOW while the address generator 4 indicates the address m in the memory 1, two instructions (m, m + 1) are fetched from the memory 1 through the fetch line 2.
Are read, and these two instructions are simultaneously read into the instruction fetch queue 3 through the jump instruction detection unit 9. Then, when the instruction output signal 8 becomes LOW, one instruction (m) out of these is output from the instruction fetch queue 3
Is supplied to the processor as. However, the remaining prefetched instructions (n + 5) are discarded as invalid instructions. The operation thereafter is the same as above.

As described above, according to the instruction prefetch apparatus of the present embodiment, since two instructions from the memories 1 and 2 are simultaneously prefetched as in the conventional case, memory access for instruction fetch is performed as compared with the case where the processor fetches one instruction at a time. The frequency decreases, and the data access to the memory 1 becomes relatively easy. Moreover, if the instruction read into the instruction fetch queue 3 includes a branch instruction,
The output of the instruction read signal 7 from the read signal generator 6 is temporarily stopped until the branch destination address of the branch instruction is determined, and the reading of the instruction from the memory 1 to the instruction fetch queue 3 is interrupted. Therefore, prefetching of the instruction at the subsequent address of the branch instruction is suppressed.

In this embodiment, the instruction fetch queue 3
Although the capacity of 5 is for 5 instructions, any capacity can be selected as long as it is for 2 instructions or more. Further, when checking whether or not a branch instruction is included in the instructions that the instruction fetch queue 3 has already read, which position in the instruction fetch queue 3 the jump instruction detection unit 9 checks is determined. It is arbitrary depending on the processing method of the branch instruction. When the jump instruction detecting unit 9 detects the reading of the unconditional branch instruction into the instruction fetch queue 3, the jump instruction detecting unit 9 itself decodes the unconditional branch instruction to determine the branch destination address, and the branch destination A configuration may be adopted in which prefetch is restarted immediately for an address.

[0030]

As described above, according to the present invention, while prefetching an instruction by advancing a plurality of instructions simultaneously from the memory to the instruction fetch queue with one access, the plurality of prefetched instructions are In the instruction prefetch device that supplies instructions from the instruction fetch queue to the processor one by one, when the instruction fetch queue prefetches a branch instruction, the prefetch is temporarily stopped until the branch destination address of the branch instruction is determined. Unnecessary prefetch of the instruction at the address subsequent to the branch instruction is suppressed, and the memory access for prefetching the instruction is minimized. Therefore, it is possible to prevent a delay in data access due to execution of unnecessary memory access for prefetch, and facilitate data access to the memory. Further, even when the instruction prefetch device according to the present invention is used in a system in which an interrupt to the processor occurs when the memory access occurs in the access prohibited area, the occurrence of the interrupt is suppressed and the processor Instruction execution performance is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an instruction prefetch device according to an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of the instruction prefetch device shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional instruction prefetch device.

FIG. 4 is a timing diagram illustrating an operation of the instruction prefetch device of FIG.

[Explanation of symbols]

 1 ... Memory 2 ... Fetch line 3 ... Instruction fetch queue 4 ... Address generator 5 ... Address line 6 ... Read signal generator 7 ... Instruction read signal 8 ... Instruction output signal 9 ... Jump instruction detector 10 ... Jump instruction detection signal 11 ... Output order

Claims (1)

Claim: What is claimed is: 1. An address generator for sequentially designating an address of an instruction to be prefetched next from a memory, and reading of instructions at a plurality of consecutive addresses starting from an address designated by the address generator. A read signal generator that sequentially outputs an instruction read signal for giving timing to the memory, and a plurality of instructions read simultaneously from the memory each time the instruction read signal is given to the memory, and the read plurality The instruction fetch queue that sequentially supplies the instructions to the processor one instruction at a time in ascending order of address, and a branch instruction that causes an address jump among a plurality of instructions read by the instruction fetch queue or a risk that an address jump may occur. Whether a branch instruction is included When the next inspection is performed and it is detected that any of the branch instructions is included, the jump instruction detecting unit that temporarily stops the output of the instruction read signal by the read signal generator until the branch destination address of the branch instruction is determined. An instruction prefetch device comprising: