KR100632317B1 - Method and system for buffering instructions in processor - Google Patents

Abstract

According to one embodiment of the invention, a method of buffering instructions in a processor having a pipeline comprising a decode stage detects stalling of the decode stage, and for instructions in the memory until the stall state of the decode stage is released. Re-issuing the prefetch and writing the fetched instructions into the instruction buffer after the stall state of the decode stage has been released.

Pipeline, decode stage, instruction buffer, program counter, memory location

Description

METHOD AND SYSTEM FOR BUFFERING INSTRUCTIONS IN A PROCESSOR}

1 is a block diagram of a computer system in accordance with the teachings of the present invention.

2 is a timing diagram illustrating the location of instructions obtained from the program memory of the computer system of FIG. 1 with respect to the various stages of the pipeline shown in FIG. 1 as an example where the pipeline is not stalled;

3 is a timing diagram illustrating the location of instructions obtained from the program memory of the computer system of FIG. 1 with respect to the various stages of the pipeline shown in FIG. 1 as an example where the pipeline is intermittently stalled.

4 is a block diagram illustrating additional details of the prefetch stage and fetch stage of the processor shown in FIG.

<Explanation of symbols for the main parts of the drawings>

10: computer system

12: processor

14: memory system

16: program memory

20: pipeline

24: prefetch stage

26: fetch stage

28: decode stage

30: reading stage

32: execution stage

34: storage stage

The present invention relates generally to a processor, and more particularly, to a method and a system for buffering instructions within a processor.

To be more efficient, most modern processors now use pipelines within the processor. Using a pipeline, tasks are divided into sequential subtasks. The division of tasks into sequential subtasks allows a large number of program instructions to be fetched, decoded and executed at any given time. Therefore, at any particular time, several instructions can be processed at various stages in the pipeline. Many such processors include a pipeline with a decode stage. At the decode stage of the pipeline, the instructions obtained from the program memory are decoded for execution. After the instructions are decoded, there is no need to store the instructions in the processor. However, until the instructions are decoded, the instructions obtained from the program memory must be stored. In order to store instructions until they are decoded, most processors use instruction buffers.

Conventional instruction buffers contain enough registers to store the same number of instructions as the stage up to the decode stage. For example, if the pipeline has the same prefetch, fetch, and decode stages as the first three stages, the associated instruction buffer would have three registers to store these three instructions. As such, when the decode stage is determined to be in a stall state, since the number of registers in the instruction buffer can be stored, the instructions being obtained are used in a conventional manner.

The use of an instruction buffer allows for resumption of processing without losing information, but this involves a problem. For example, as the common instruction fetches increase in size, each register in the instruction buffer increases in size, requiring additional silicon regions.

Thus, there is a need for an improved method and system for buffering instructions in a processor. The present invention provides a system and method for buffering instructions in a processor for the purpose of solving the disadvantages of conventional systems and methods.

According to one embodiment of the invention, a method of buffering instructions in a processor with a pipeline having a decode stage detects stalling of the decode stage and advances to instructions in memory until the stall state of the decode stage is released. Reissuing the fetch, and then writing the fetch instruction into the instruction buffer after the stall state of the decode stage is released.

According to another embodiment of the present invention, the processor pipeline includes a plurality of sequential stages before the decode stage, and a limited instruction buffer capable of simultaneously storing instructions having a number less than or equal to the number of sequential stages. The processor pipeline also includes a counter system. The counter system includes a counter for storing a count specifying an address of a memory location that stores instructions received in a limited instruction buffer. The counter system may also adjust the count of the counter based on the state of the decode stage. The plurality of sequential stages includes a fetch stage that can fetch an instruction at an address specified by a count.

Embodiments of the present invention have many technical advantages. For example, in one embodiment of the present invention, a limited instruction buffer may be used instead of the conventional larger instruction buffer to buffer fetch instructions from program memory. The smaller sized limited instruction buffer shrinks the silicon area to make the device smaller, and allows such silicon area to be used in other areas of the processor.

Those skilled in the art will readily recognize other technical features from the accompanying drawings, the specification and the claims.

Embodiments of the present invention and their advantages can be better understood with reference to FIGS. 1 to 4, wherein like corresponding parts in the various figures use the same reference numerals.

1 is a block diagram of a processor in accordance with the teachings of the present invention. Computer system 10 includes a processor 12 and a memory system 14. The processor 12 may operate as an access memory system 14. Memory system 14 may include both program memory 16 and data memory 16. The processor 12 includes a pipeline 20. The pipeline 20 includes a prefetch stage 24, a fetch stage 26, a decode stage 28, a read stage 30, an execution stage 32 and a storage stage 34. The processor 12 may also include additional processing elements 21.

Prefetch stage 24 determines the address of the memory location in program memory 16 to read the instruction. Fetch stage 26 reads the instructions at the program memory location determined by prefetch stage 24. Fetch stage 24 includes a limited instruction buffer 50 to buffer fetch instructions from program memory 16. The limited instruction buffer 50 is shown in FIG. 4. In the present embodiment, the limited instruction buffer 50 includes a first register 52 and a second register 54. In accordance with the present invention, the limited instruction buffer 50 includes the same number of registers as the number of stages in the pipeline 20 prior to the decode stage 28, two in this embodiment.

Decode stage 28 decodes the instructions obtained from program memory 16. The read stage 30 reads from the data memory 18 the data necessary for the execution of the decoded instructions by the decode stage 28. Read stage 30 may be replaced with one or more stages. For example, read stage 30 may be replaced by a separate stage that performs the necessary calculations to determine the location in data memory 18 where data is to be read and a separate stage that performs the function of reading such data. The execution stage 32 performs the function of executing the instructions decoded by the decode stage 28. The storage stage 34 consequently performs the function of recording certain data which may be required to be written after the instruction is executed.

The use of a limited instruction buffer with the same number of registers as the number of stages preceding the decode stage 28 reduces the silicon area requirement for the processor 12. The reduction in silicon area requirements for the processor 12 is generally an advantage. According to the present invention, the limited instruction buffer reissuing instructions fetches in the program memory 16, without consequently losing processor performance, as described in detail below with reference to FIGS. Can be used.

FIG. 2 is a timing diagram illustrating the location of instructions obtained from program memory 16 with respect to various stages of pipeline 20, as an example where pipeline 20 is not stalled. In normal processing, processor 12 continuously fetches instructions from locations in program memory 16 having sequential execution addresses. If for some reason processor 12 is stalled, processor 12 continues to fetch instructions from program memory 16. For example, the processor 12 may be in a stall state while waiting to receive data from the data memory 18. In such a case, the limited instruction buffer 50 may accumulate two instructions while waiting for resume processing. The operation of the prefetch stage 24, fetch stage 26 and decode stage 28, combined with the limited instruction buffer 50, is described below with reference to FIG. 2 for an example where no stall state occurs.

During the first clock period, the address for the memory location corresponding to the first instruction I ₁ is calculated. During the second clock period, the address for the second instruction I ₂ is calculated and the fetching of the instruction I ₁ is initiated. During the third clock period, the address for the memory location corresponding to the third instruction I ₃ is calculated, the fetching of the instruction I ₁ is completed, the fetching of I ₂ is started, and the processor 12 is not in the stall state. Decoding of the instruction I ₁ is started and completed.
During the third clock period, the register 52 of the restricted instruction buffer 50 stores the instruction I ₁ . The restricted instruction buffer 50 includes a pointer 56 that specifies a register in the restricted instruction buffer 50 that stores the current instruction to be decoded. Instruction pointer 56 is shown in FIG. 4 as a pointing to register 52. During this third clock period, pointer 56 designates register 52. During the fourth clock period, the address for the fourth instruction I ₄ is calculated, the fetching of the instruction I ₂ is completed, the fetching of the instruction I ₃ is started, and the decoding of the instruction I ₂ is started and completed. During the fourth clock period, register 52 continues to store instruction I ₁ because register I ₁ was not overwritten by another instruction, register 54 stores instruction I ₂ , and pointer 56 ) Designates the register 54.

During the fifth clock period, the address for the fifth instruction I ₅ is calculated, the fetching of the instruction I ₃ is completed, the fetching of the instruction I ₄ is started, and the decoding of the instruction I ₃ is started and completed. During the fifth clock period, instruction I ₃ is stored in register 52, and pointer 56 of restricted instruction buffer 50 designates register 52. During the sixth clock period, the address for the sixth instruction I ₆ is calculated, the fetching of the instruction I ₄ is completed, the fetching of the instruction I ₅ is started, the decoding of the instruction I ₄ is started and completed, and the instruction I ₃ All data associated with is read. During the sixth clock period, instruction I ₄ is stored in register 54 and pointer 56 of restricted instruction buffer 50 designates register 54.

In the above-described order of obtaining and processing instructions, the limited instruction buffer 50 stores the instruction in one of two registers 52, 54 where the instruction is to be decoded. Since the processor 12 is not stalled in the order described above, the limited instruction buffer 50 is sufficient to continue to fetch additional sequential instructions without having to reissue the fetch. The operation of the processor 12 during intermittent stall periods is described with reference to FIG.

3 is a timing diagram illustrating the location of instructions obtained from program memory 16 for various stages of pipeline 20 as an example where the stall state of pipeline 20 occurs intermittently. The operations of prefetch stage 24, fetch stage 26, decode stage 28, and limited instruction buffer 50 are described for an example where intermittent stalls occur in pipeline 20. During the first clock period, the address for the first instruction I ₁ is calculated. As shown in the last row of FIG. 3, no stall of the processor 12 occurs during this first clock period. During the second clock period, the address for the second instruction I ₂ is calculated and the fetching of the instruction I ₁ is initiated. During the third clock period, the address for the third instruction I ₃ is calculated, the fetching of the instruction I ₁ is completed, the fetching of the instruction I ₂ is started, and the decoding of the instruction I ₁ is started. In this example, the decode stage 28 is stalled during the third clock period, so that decoding of the instruction I ₁ is not completed during the third clock period. As used herein, the stall of decode stage 28 is the actual stall state of decode stage 28 or another stage in pipeline 20 that prevents decode stage 28 from decoding the next instruction. The stall state. For example, such a stall state occurs due to the stall state of the read stage 30 in the memory read operation. For three clock periods, the instruction I ₁ is stored in register 52, and pointer 56 designates register 52.

During the fourth clock period, since the decode stage 28 was stalled in the previous clock period, no additional address associated with the next instruction is calculated. The fetching of the instruction I ₂ is completed and the fetching of the instruction I ₃ is started. Since the decode stage 28 remains stalled, decoding of the instruction I ₁ continues, but is not complete. During this fourth clock period, instruction I ₁ remains in register 52, instruction I ₂ is stored in register 54, and pointer 56 remains with register 52 specified.

During the fifth clock period, since the decode stage 28 was stalled in the previous clock period, no additional address is calculated for the additional instruction. In addition, because the limited instruction buffer 50 is full, the fetching of the instruction I ₃ cannot be terminated because the instruction I ₃ cannot be stored in the instruction buffer 50. Therefore, instruction I ₃ is discarded, and the fetching of instruction I ₃ is resumed during this fifth clock period. Since the decode stage 28 is no longer stalled, the decoding of the instruction I ₁ is completed during the fifth clock period. Conventional processor, rather than to discard the instruction I _3, and re-issue a fetch for the instruction I _3, was a third register in the instruction buffer for storing an instruction I _3. The present invention does not require such a register, thus reducing the need for silicon regions. During the fifth clock period, register 52 stores instruction I ₁ , register 54 stores instruction I ₂ , and pointer 56 designates register 52.

In the sixth clock period, the decode stage 28 is no longer stalled. Therefore, the address for the fourth instruction I ₄ is calculated, the fetching of the instruction I ₃ is completed, and the decoding of the instruction I ₂ is started and completed. During this sixth clock period, instruction I ₃ is stored in register 52, instruction I ₂ is stored in register 54, and pointer 56 designates register 54.

As such, in the example described in FIG. 3 where an intermittent stall occurs in the pipeline 20, an instruction whose address is computed when the pipeline 20 is in the stall state until the stall state of the pipeline is released. It is issued continuously. Therefore, the present invention avoids the need for an instruction found at the address being calculated when the pipeline first enters the stall state, i.e., an instruction buffer having a third register that stores the instruction I ₃ in the above embodiment. . Avoiding the need for such a register in the instruction buffer may help reissue a fetch instruction, such as instruction I ₃ , when pipeline 20 is stalled. An example of physically implementing the aforementioned method for processing an instruction is described below with reference to FIG. 4.

4 is a block diagram illustrating additional details of the prefetch stage 24 and the fetch stage 26 of the processor 12. As shown, the prefetch stage 24 includes a program counter 58 and a multiplexer 60. Program counter 58 holds a current count to specify a location in memory system 14 that receives instructions. The multiplexer 60 receives the previous count of the program counter 58, and the previous count of the program counter 58 is incremented by one as an input signal. Multiplexer 60 generates output signal 62 that provides an updated count for program counter 58. The multiplexer 60 is controlled by the select signal 64 received from the decode stage 28. When the decode stage 28 goes into a stall state due to the stalling of the decode stage 28 itself or the stall stage of the downstream stage of the decode stage 28 in the pipeline 20, the selection signal 64 Selects the value of the preceding program counter 58, and when the decode stage 28 is not in the stall state, the output signal 62 selects the count of the preceding program counter 58 incremented by one. Next, the output signal 62 is provided to the program counter 58. In this manner, when the decode stage 28 is in the stall state, the most recent instruction whose address was computed by the prefetch stage 24 is fetched continuously until the stall state of the decode stage 28 is released. .

As mentioned above, the present invention reduces the silicon area to make the device more compact, since the limited instruction buffer can be used instead of the conventional larger instruction buffer to buffer fetch instructions from the program memory, and other areas of the processor. It is possible to use such a silicon region within.

While the invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (12)

A method of buffering instructions in a processor having a pipeline comprising a decode stage, the method comprising: Detecting stalling of the decode stage; Ressuing a prefetch for instructions in memory until the stall state of the decode stage is released in response to the stalling detection of the decode stage; And Writing the fetched instruction into an instruction buffer after the stall state of the decode stage is released How to include. 2. The method of claim 1, further comprising determining whether the instruction buffer is full. 3. The method of claim 2, wherein the refetching of the prefetch comprises reissuing a prefetch for an instruction stored in a memory only when the instruction buffer is full. 2. The method of claim 1, wherein the prefetch reissue step comprises fetching an instruction stored at a memory location having an address specified by a count of a program counter. 5. The method of claim 4, wherein the prefetch reissue step comprises adjusting a count of the program counter from there to a count corresponding to an address of the memory location to which the instruction was prefetched. 6. The method of claim 5, wherein the prefetch reissue step includes leaving the count of the program counter unchanged. The method of claim 1, wherein the pipeline comprises a plurality of sequential stages prior to the decode stage, and wherein writing the fetched instructions to an instruction buffer is equal to or less than the number of sequential stages preceding the decode stage. Writing the fetched instructions to an instruction buffer operable to store the number of instructions concurrently. In the processor pipeline, A plurality of sequential stages preceding the decode stage; A limited instruction buffer operable to simultaneously store instructions having a number equal to or less than the number of sequential stages; A counter system for storing a count specifying an address of a memory location that stores instructions received by the restricted instruction buffer, the counter system operable to adjust the count of the counter based on a state of the decode stage; And A plurality of sequential stages including a fetch unit operable to fetch the instruction at the address specified by the count Processor pipeline comprising a. The counter system of claim 8, wherein the counter system is configured to increment the count of the counter when the decode stage is in the stall state, and to leave the count of the counter unchanged when the decode stage is not in the stall state. Processor pipeline. The counter system of claim 8, wherein the counter system decrements the count of the counter when the decode stage is not in a stall state, and does not change the count of the counter when the decode stage is in a stall state. Processor pipeline operable to leave. 9. The processor pipeline of claim 8, wherein the counter system further comprises a multiplexer operable to receive a control signal indicative of the state of the decode stage. 12. The apparatus of claim 11, wherein the multiplexer is operable to receive a count of the counter and an incremented count of the counter, the output signal representing either one of the count of the counter and the incremented count of the counter. A processor pipeline operable to generate based on the control signal indicative of a state of the decode stage.

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