JPS63314644A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the reading time of a loop instruction and to carry out the loop instruction at a high speed with use of the repetitive execution characteristics of the loop instruction, by performing the automatic switch between an instruction queue and a loop instruction queue and at the same time extracting the instruction codes stored in both queues. CONSTITUTION:Each loop instruction is registered into a loop instruction queue 3-1. The automatic switch is carried out between an instruction queue 2 and the queue 3-1 and at the same time the instruction codes are extracted out of both queues so that the reading cycle is omitted for instructions stored in a loop. Thus it is possible to omit an action to read repetitively the loop instructions out of a memory and to shorten the reading time of the loop instructions. Then the loop instruction is carried out at a high speed with use of the repetitive execution characteristics of the loop instruction.

Description

TECHNICAL FIELD The present invention relates to a data processing device, and more particularly to instruction advance read control for a data processing device having an instruction queue for reading and storing preceding instructions.

BACKGROUND OF THE INVENTION Conventionally, in data processing apparatuses, instruction advance reading control has been performed such that instructions read in advance are sequentially stored in an instruction queue.

In such conventional data processing devices, a group of instructions forming a loop is read every time and stored in an instruction queue like other instructions, and these instructions are sequentially decoded and decoded according to control. Since the instruction is sent to the instruction execution unit, this instruction pre-read control has the disadvantage that high-speed execution cannot be realized by utilizing the repeated execution characteristic of a loop.

OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional method.The present invention is capable of reducing the read time of loop instructions, and is capable of reducing the read time of loop instructions by utilizing the characteristic of repeated execution of loop instructions. The purpose of the present invention is to provide a data processing device that can realize high-speed execution.

Structure of the Invention A data processing device 2 according to the present invention is a data processing device having an instruction queue for reading and storing a preceding instruction, and a loop instruction queue for storing a group of instructions constituting a loop; and a detection means for detecting that the added additional information is an instruction to store the instruction group in the loop instruction queue, and stores the instruction group in the loop instruction queue according to the detection result of the detection means. It is characterized by the following.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a data processing device according to an embodiment of the present invention is
A prefetch instruction register 1 that temporarily stores the contents of the system bus 11, a normal instruction queue 2, and a plurality of loop instruction queues 3-i (i=1.2..., n
), a preceding instruction decoder 4 that instructs each instruction queue to set and generates information, and an instruction queue output control circuit 5 that selects the output from each instruction queue storage section and sends it to the internal bus 12. There is.

When the previously read instruction is set in the brief fetch instruction register 1, the preceding instruction decoder 4 determines the ]-code of that instruction.

If this code is a loop instruction queue registration instruction, that is, an instruction provided at the beginning of a loop instruction and for registering a group of instructions constituting the loop instruction in the loop instruction queue 3-i, the specified loop instruction queue 3-i contains the number of words (the number of steps constituting the loop) specified in i, and the loop instruction to be executed next as additional information added to the instruction immediately before the loop instruction stored in instruction queue 2. The number of the loop instruction queue 3-i in which the is stored is written.

A normal instruction queue 2 stores instructions read out one after another and its contents are updated, but a loop instruction queue 3-i is not updated unless a loop instruction queue registration instruction is executed. A plurality of loop instructions are registered in the loop instruction queue 3-i by this loop instruction queue registration instruction.

When an instruction code is taken out from each instruction queue for instruction interpretation and execution, it is usually taken out from the instruction queue 2 side, but the instruction execution order information part (
(not shown), the next instruction is fetched from the loop instruction queue 3-i.
If fetching from the side is specified, the loop instruction queue 3- of the number written as additional information at the time of the specification is specified.
A loop instruction is extracted from i and this loop instruction is executed.

By executing loop instructions, if a preset loop end flag is detected when the loop instruction is registered in the loop instruction queue 3-i, the instruction code is extracted from the instruction queue 2 side. It is now back to .

Furthermore, each loop instruction registered in the loop instruction queue 3-i can be used any number of times as long as it is not updated.

In this way, each loop instruction is registered in the loop instruction queue 3-i, and the instruction code stored in the instruction queue 2 and the loop instruction queue 3-i is retrieved while automatically switching between the instruction queue 2 and the loop instruction queue 3-i. By omitting the read cycle of the instructions in the loop, the operation of repeatedly reading from a memory (not shown) becomes unnecessary, and the read time of the loop instructions can be reduced. This makes it possible to realize high-speed execution of loop instructions by utilizing the characteristic of repeated execution of loop instructions.

According to the present invention, as described in detail, a loop instruction queue is provided for storing a group of instructions constituting a loop, and the instructions are stored in the instruction queue and the loop instruction queue while being automatically switched between the instruction queue and the loop instruction queue. By extracting the instruction code, the time required to read the loop instruction can be reduced, and the loop instruction can be executed at high speed by taking advantage of the repeated execution characteristics of the loop instruction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of codes of main parts 1...Briefetch instruction register 2...
・Instruction queue

Claims (1)

[Claims] A data processing device having an instruction queue for reading and storing preceding instructions, the loop instruction queue storing a group of instructions constituting a loop, and a loop instruction queue for storing a group of instructions forming a loop, and a loop instruction queue for storing a group of instructions constituting a loop; 1. A data processing apparatus, comprising: a detection means for detecting that the instruction is an instruction to be stored in an instruction queue, and the instruction group is stored in the loop instruction queue according to a detection result of the detection means.