JPH0553798A - Information processor - Google Patents

Abstract

PURPOSE:To shorten waiting time for an instruction language block load to a cache at the time of a cache mistake hit. CONSTITUTION:When the cache mistake hit is detected in a hit detecting circuit 8, a block load instruction circuit 11 generates instruction for taking-out an erroneously hitted instruction language block from a main storing device. During the block load, a succeeding block address generating circuit 3 generates a succeeding block address so as to index address array 7. When the succeeding block is the mistake hit and also there is not branching instruction in whole instruction after detecting the presence or absence of branching in instruction within the present block loads by a branching instruction judging circuit 4, the succeeding block load is instructed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly to a control system for an instruction word cache circuit that stores a part of an instruction word stored in a main storage device in block units.

[0002]

2. Description of the Related Art In this type of instruction word cache circuit, when all the instructions of an instruction word block that causes a cache hit are fetched from the cache and a mishit occurs when the next instruction word block is fetched from the cache, the main memory device The fetch of the block of the instruction word that has a mis-hit is started.

In such a conventional cache circuit, the next mishit block is fetched from the main storage device after fetching all the instructions of the instruction word block that has made a cache hit from the cache. There is a disadvantage that the processing of the instruction word of the next block cannot be started until the block loading of the instruction word (registration of the instruction word block in the cache) is completed, and therefore the waiting time between them is long.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an information processing apparatus capable of shortening the instruction word block load waiting time at the time of a cache miss.

[0005]

An information processing apparatus according to the present invention comprises a main memory device, a cache circuit for storing a part of an instruction word stored in the main memory device in block units, and an instruction word block address for the cache circuit. Hit detecting means for detecting a cache hit state in response to the index by the cache detecting means, and an instruction word block at the time of a cache miss hit from the main memory device in response to the detection of the cache miss hit by the hit detecting means to the cache circuit. Control means for instructing the loading of data, a next block indexing means for indexing the cache circuit by generating a next instruction word block address during the load operation, and an instruction word in the instruction word block fetched from the main memory device. Branch instruction determining means for determining the presence or absence of a branch instruction while sequentially decoding the At the end, when the hit detection means detects a mishit and the branch instruction determination means determines that there is no branch instruction, the control means is instructed to take out the next instruction word block from the main storage means. And means.

[0006]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The information processing apparatus of the present invention includes an address register 1 for holding an instruction fetch address 100 for fetching an instruction word, a block data register 2 for holding block data 101 for one clock, and a next block address for generating a next block address when a cache miss occurs. A branch instruction determination circuit 4 for determining whether all the instruction words in the generation circuit 3 and the fetch block 104 are sequential branch instructions, a normal index address 103
And an address selection circuit 5 for selecting one of the next block address at the time of a mishit, an instruction word data array 6 for holding the data of the cache circuit in block units, an instruction word address array 7 for holding the corresponding address, and a cache hit. A cache hit detection circuit 8 for detecting the output 107 of the instruction word address array 7 and the cache key address 102, a second flip-flop 9 for holding whether or not the next block is in the cache, and a branch instruction in the fetch block are shown. The third flip-flop 10,
A block load instruction circuit 11 for generating an instruction signal 112 for instructing the fetching of a block from a main memory (not shown),
It has a first flip-flop 12 which holds a take-out instruction signal 112 of this block.

The operation of the embodiment of the present invention will be described below with reference to the time chart of FIG.

At the time of fetching the command word, whether the command word fetch address 100 of the command word fetch address is held in the command fetch address register 1, and whether the command word data array 6 containing the command word data and the command word data exist in the cache. The instruction word address array 7 containing the information is indexed by the cache index address 103. At this time, the address selection circuit 5 selects the cache index address 103.

Whether the command word output 108 of the command word data in the indexed cache is valid is judged by the cache hit detection circuit 8, and in the case of a cache hit, the command word is derived as the command word output 108.

In the case of a cache mishit, the block load instructing circuit 11 produces a fetch instructing signal 112 from the main memory of the mishit block by the mishit signal of the cache hit signal 109 and the first flip-flop 12
Hold on.

After that, the address of the next block created by the next block address generation circuit 3 is set to the address selection circuit 5.
The address 105 of the next block is indexed by the output 105 of the address selection circuit 5. This next block address is "n + 1" if the value of the current address 103 is "n".

Output of indexed instruction word address array 7
Based on 107 and the cache key address 102, the cache hit detection circuit 8 determines whether or not the next block is in the cache, and holds the result 109 in the second flip-flop 9.

The data of the mishit block which has previously become a mishit is fetched from the main memory and sequentially held in the block data register 2 as the block data 101. At this time, data is written in the instruction word data array 6 and the branch instruction determination circuit 4 determines whether or not there is a branch instruction. The output 106 of the branch instruction determination circuit 4, which is a signal indicating whether or not there is a branch instruction, is held in the third flip-flop 10.

When the second flip-flop 9 at this point indicates a mishit of the next block and the third flip-flop 10 indicates that there is no branch instruction in the fetched block, the block load instructing circuit 11 indicates the next instruction. A block take-out instruction signal is created.

If the second flip-flop 9 indicates the next block hit or the third flip-flop 10 indicates the presence of a branch instruction in the fetched block,
The block load instruction circuit 11 does not create a fetch instruction signal for the next block.

[0017]

As described above, according to the present invention, at the time of a mishit, the instruction word is discriminated before the block is loaded into the cache, and if there is no branch instruction, the fetch of the next mishit block is immediately instructed. This has the effect of reducing the waiting time for loading the next block.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 1 instruction word fetch address register 2 block data register tertiary block address generation circuit 4 branch instruction determination circuit 5 address selection circuit 6 instruction word data array 7 instruction word address array 8 cache hit detection circuit 9, 10, 12 flip-flop 11 block load Indicator circuit

Claims (1)

[Claims] 1. A cache hit in response to a main memory device, a cache circuit for storing a part of an instruction word stored in the main memory device in block units, and an index by an instruction word block address for the cache circuit. Hit detecting means for detecting a state; and control means for, in response to the detection of the cache miss hit by the hit detecting means, fetching an instruction word block at the time of the cache miss hit from the main storage device and instructing a load to the cache circuit. , A next block index means for generating a next instruction word block address during the load operation to index the cache circuit, and a branch instruction while sequentially decoding the instruction words in the instruction word block fetched from the main memory device. Branch instruction determining means for determining the presence or absence, and at the end of extracting the instruction word block,
Means for instructing the control means to fetch the next instruction word block from the main memory means when the hit detection means detects a mishit and the branch instruction determination means determines that there is no branch instruction. An information processing device comprising: