JPS57100699A - Detector for irregular main storage address - Google Patents

Detector for irregular main storage address

Info

Publication number
JPS57100699A
JPS57100699A JP55176691A JP17669180A JPS57100699A JP S57100699 A JPS57100699 A JP S57100699A JP 55176691 A JP55176691 A JP 55176691A JP 17669180 A JP17669180 A JP 17669180A JP S57100699 A JPS57100699 A JP S57100699A
Authority
JP
Japan
Prior art keywords
main
main storage
irregular
address
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55176691A
Other languages
Japanese (ja)
Inventor
Kanji Tsuchiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55176691A priority Critical patent/JPS57100699A/en
Publication of JPS57100699A publication Critical patent/JPS57100699A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the complexity of switch setting and to detect an irregular main storage address at a high speed, by providing a register for irregular-main-storage-address detection in a main storage controller.
CONSTITUTION: A CPU, when a power source is put to work, reads the contents of each main storage device MEM1Wi and checks the presence of main- storage-device presence signal ADHL at this time. Then, an irregular main storage address setting register DFF is reset when the main storage device is present and set when not. After the package state of the main storage device is set in the DFF, a main storage controller MCU generates an irregular-main- storage-address detection signal C on the basis of main storage device selection signals A and B and information in the DFF. Consequently, the irregular main storage address is detected with minimum line length, detection time is minimized and the setting ofan irregular-main-storage-address setting switch becomes unnecessary.
COPYRIGHT: (C)1982,JPO&Japio
JP55176691A 1980-12-15 1980-12-15 Detector for irregular main storage address Pending JPS57100699A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55176691A JPS57100699A (en) 1980-12-15 1980-12-15 Detector for irregular main storage address

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55176691A JPS57100699A (en) 1980-12-15 1980-12-15 Detector for irregular main storage address

Publications (1)

Publication Number Publication Date
JPS57100699A true JPS57100699A (en) 1982-06-22

Family

ID=16018041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55176691A Pending JPS57100699A (en) 1980-12-15 1980-12-15 Detector for irregular main storage address

Country Status (1)

Country Link
JP (1) JPS57100699A (en)

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