JPS6468858A - Microprocessor peripheral circuit - Google Patents
Microprocessor peripheral circuitInfo
- Publication number
- JPS6468858A JPS6468858A JP62226176A JP22617687A JPS6468858A JP S6468858 A JPS6468858 A JP S6468858A JP 62226176 A JP62226176 A JP 62226176A JP 22617687 A JP22617687 A JP 22617687A JP S6468858 A JPS6468858 A JP S6468858A
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- ready signal
- access
- reach
- peripheral circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To enable a microprocessor to perform the normal operation, by outputting a second ready signal from a ready signal monitoring circuit to terminate the access of the microprocessor when a first ready signal does not reach the microprocessor over a fixed time. CONSTITUTION:A ready signal monitoring circuit 4 is provided, and this circuit 4 outputs a second ready signal 16 when a first ready signal 15 from a ready signal generating circuit 3 does not reach a microprocessor 1 though a prescribed time elapses after the start of the access from the microprocessor 1 to the access object device such as a memory. The microprocessor 1 terminates the current access by the second ready signal 16 even if the first ready signal 15 does not reach the microprocessor 1. Thus, the microprocessor is prevented from stopping the operation as conventional.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62226176A JPS6468858A (en) | 1987-09-09 | 1987-09-09 | Microprocessor peripheral circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62226176A JPS6468858A (en) | 1987-09-09 | 1987-09-09 | Microprocessor peripheral circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6468858A true JPS6468858A (en) | 1989-03-14 |
Family
ID=16841075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62226176A Pending JPS6468858A (en) | 1987-09-09 | 1987-09-09 | Microprocessor peripheral circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6468858A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0469754A (en) * | 1990-07-11 | 1992-03-04 | Nec Data Terminal Ltd | Access time monitoring system |
US7243257B2 (en) | 2002-05-14 | 2007-07-10 | Nec Corporation | Computer system for preventing inter-node fault propagation |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5543682A (en) * | 1978-09-22 | 1980-03-27 | Hitachi Ltd | Input/output unit control system |
JPS5583948A (en) * | 1978-12-19 | 1980-06-24 | Mitsubishi Electric Corp | Microprocessor system |
JPS57728A (en) * | 1980-05-30 | 1982-01-05 | Mitsubishi Electric Corp | Monitoring device |
JPS6121553A (en) * | 1984-07-04 | 1986-01-30 | Fujitsu Ltd | Ready state informing system to processor |
-
1987
- 1987-09-09 JP JP62226176A patent/JPS6468858A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5543682A (en) * | 1978-09-22 | 1980-03-27 | Hitachi Ltd | Input/output unit control system |
JPS5583948A (en) * | 1978-12-19 | 1980-06-24 | Mitsubishi Electric Corp | Microprocessor system |
JPS57728A (en) * | 1980-05-30 | 1982-01-05 | Mitsubishi Electric Corp | Monitoring device |
JPS6121553A (en) * | 1984-07-04 | 1986-01-30 | Fujitsu Ltd | Ready state informing system to processor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0469754A (en) * | 1990-07-11 | 1992-03-04 | Nec Data Terminal Ltd | Access time monitoring system |
US7243257B2 (en) | 2002-05-14 | 2007-07-10 | Nec Corporation | Computer system for preventing inter-node fault propagation |
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