KR970022341A

KR970022341A - Serial flip-flop test time saver

Info

Publication number: KR970022341A
Application number: KR1019950034916A
Authority: KR
Inventors: 박성근
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-10-11
Filing date: 1995-10-11
Publication date: 1997-05-28

Abstract

본 발명은 플립플롭의 테스트에 관한 것으로서, 특히 연속하여 접속된 플립플롭의 테스트 시간 절감 장치에 관한 것이다.The present invention relates to the testing of flip-flops, and more particularly, to an apparatus for reducing test time of flip-flops connected in series.

마이크로 킴퓨터에 내장된 시리얼 플립플롭 테스트 시간 절감장치는 마이크로 컴퓨터내에 홀트 테스트시에 병행하여 시리얼 플립플롭의 일부를 테스트하고 홀트 테스트 후 나머지 시리얼 플립플롭의 처음 플립플롭단에 발진클럭을 인가시켜 최종 시리얼 플립플롭 출력단자에서 출력신호를 테스트하여 플립플롭의 이상 유무를 테스트한다.The serial flip-flop test time saver built into the micro-kimputer test part of the serial flip-flop in parallel during the Holt test in the microcomputer, and apply the oscillation clock to the first flip-flop end of the remaining serial flip-flop after the Holt test. Test the output signal at the serial flip-flop output terminal to test the flip-flop for abnormality.

따라서, 본 발명에 따른 마이크로 컴퓨터에 내장된 시리얼 플립플롭 테스트 시간 절감 장치는 마이크로 컴퓨터의 홀트 테스트와 병행하여 시리얼 플립플롭을 테스트하고 나머지 플립플롭을 테스트함으로써 시리얼 플립플롭의 테스트 시간을 대폭 단축시켜 마이크로 컴퓨터의 생산비를 절감하는 효과를 제공한다.Therefore, the serial flip-flop test time reduction apparatus built in the microcomputer according to the present invention greatly reduces the test time of the serial flip-flop by testing the serial flip-flop and testing the remaining flip-flop in parallel with the hold test of the micro-computer. It can reduce the production cost of computer.

Description

Serial flip-flop test time saver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 마이크로 컴퓨터에 내장된 시리얼 플립플롭의 테스트를 설명하기 위한 블럭도이다,1 is a block diagram illustrating a test of a serial flip-flop embedded in a conventional microcomputer.

제2도는 제1도에 부가되는 본 발명에 따른 마이크로 컴퓨터에 내장된 시리얼 플립플롭의 테스트를 설명하기 위한 블럭도이다.2 is a block diagram illustrating a test of a serial flip-flop embedded in a microcomputer according to the present invention, which is added to FIG.

Claims

1. A serial flip-flop test time reduction apparatus embedded in a microcomputer, comprising: N flip-flops connected in series; An oscillator connected to an initial flip-flop clock input terminal and a clock input unit of the N flip-flops; A holt test unit for testing a holt by detecting an output level of an inverter output terminal of a flip-flop at a predetermined intermediate position among the N flip-flops; A test and oscillation signal is connected to the inverter clock terminal of the next flip-flop connected to the flip-flop at the predetermined intermediate position by an AND gate, and one output of the gate is connected to the inverter clock terminal through the inverter. An intermediate dustproof output input unit applying a click to the clock terminal; An automatic reset unit configured to test flip-flops at the rear end of the flip-flop at the predetermined intermediate position by applying a predetermined clock from the intermediate oscillation output input unit after the holt test and then connecting to the last output terminals of the N flip-flops. Serial flip-flop test time saving device characterized in that.

※ Note: The disclosure is based on the initial application.