KR930010686A - I / O device access timing setting device - Google Patents
I / O device access timing setting device Download PDFInfo
- Publication number
- KR930010686A KR930010686A KR1019910020531A KR910020531A KR930010686A KR 930010686 A KR930010686 A KR 930010686A KR 1019910020531 A KR1019910020531 A KR 1019910020531A KR 910020531 A KR910020531 A KR 910020531A KR 930010686 A KR930010686 A KR 930010686A
- Authority
- KR
- South Korea
- Prior art keywords
- shift register
- access timing
- timing setting
- ibm
- speed
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
본 발명은 IBM-PC AT(Advanced Technology)급 이상의 시스템을 적용하는 장치에 있어서, 동작속도가 저속인 입/출력장치를 시스템에 인터페이스하고자 할 경우 IBM-PC의 시스템 클록에 웨이트스테이트(Wait State)를 삽입하여 I/O주기를 연장시킴으로써 I/O디바이스의 엑세스타이밍에 셋팅할 수 있는 I/O디바이스의 엑세스타이밍 셋팅 장치에 관한 것으로서, 2진정보를 필요에 따라 좌우로 자리이동시킴으로써 I/O체크준비 신호를 인가하는 시프트레지스터와, 상기 시프트레지스터에 입력되는 낸드게이트를 통과한 I/O디바이스 선택 입력신호를 쇼트상태에 따라 인버터를 통과시켜서 좀더 고속으로 또는 좀더 저속으로 시프트레지스터에 재 입력시키는 딥스위치로 이루어진 것을 특징으로 한다.The present invention is a device that applies IBM-PC Advanced Technology (AT) or higher system, the weight state (Wait State) to the system clock of the IBM-PC when you want to interface the input / output device with a low operating speed to the system An access timing setting device for an I / O device that can be set for access timing of an I / O device by inserting an I / O period to extend the I / O cycle. A shift register for applying a check ready signal and an I / O device selection input signal passing through the NAND gate input to the shift register are passed through the inverter according to the short state to be re-entered into the shift register at a higher speed or at a lower speed. It is characterized by consisting of a dip switch.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 실시예에 따른 회로도,1 is a circuit diagram according to an embodiment of the present invention,
제2도는 본 발명에 사용되는 시프트레지스터의 단자 상태도.2 is a terminal state diagram of a shift register used in the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910020531A KR940008855B1 (en) | 1991-11-18 | 1991-11-18 | Access timing setting apparatus for i/o device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910020531A KR940008855B1 (en) | 1991-11-18 | 1991-11-18 | Access timing setting apparatus for i/o device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930010686A true KR930010686A (en) | 1993-06-23 |
KR940008855B1 KR940008855B1 (en) | 1994-09-28 |
Family
ID=19323017
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910020531A KR940008855B1 (en) | 1991-11-18 | 1991-11-18 | Access timing setting apparatus for i/o device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940008855B1 (en) |
-
1991
- 1991-11-18 KR KR1019910020531A patent/KR940008855B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR940008855B1 (en) | 1994-09-28 |
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E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
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FPAY | Annual fee payment |
Payment date: 19970829 Year of fee payment: 6 |
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