KR930020843A - Clock signal selection circuit - Google Patents

Clock signal selection circuit Download PDF

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Publication number
KR930020843A
KR930020843A KR1019920003642A KR920003642A KR930020843A KR 930020843 A KR930020843 A KR 930020843A KR 1019920003642 A KR1019920003642 A KR 1019920003642A KR 920003642 A KR920003642 A KR 920003642A KR 930020843 A KR930020843 A KR 930020843A
Authority
KR
South Korea
Prior art keywords
clock
selection circuit
clock signal
signal selection
decoder
Prior art date
Application number
KR1019920003642A
Other languages
Korean (ko)
Inventor
열 이
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019920003642A priority Critical patent/KR930020843A/en
Publication of KR930020843A publication Critical patent/KR930020843A/en

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Abstract

클럭신호 선택회로는 컴퓨터등의 장치가 2이상의 크럭을 가지는 경우에 프로그램에 의하여 1클럭을 선택하여 사용할 수 있게하는 회로이다. 상이한 클럭속도를 가지는 2이상의 클럭을 갖추고 있는 장치에 있어서, 클럭신호 선택회로는 외부로부터 수신된 클럭선택신호를 저장하는 레지스터, 레지스터로부터의 클럭선택신호 출력을 디코딩하기 위한 디코더, 클럭의 출력단자에 접속되며 디코더의 출력단자에 각각 접속되는 버퍼수단을 포함한다.The clock signal selection circuit is a circuit that allows one clock to be selected and used by a program when a device such as a computer has two or more clocks. In an apparatus having two or more clocks having different clock speeds, the clock signal selection circuit includes a register for storing a clock selection signal received from an external device, a decoder for decoding a clock selection signal output from the register, and a clock output terminal. And buffer means connected to each output terminal of the decoder.

Description

클럭신호 선택회로Clock signal selection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 클럭신호 선택회로의 회로도.1 is a circuit diagram of a clock signal selection circuit according to the present invention.

제2도는 본 발명에 따른 클럭신호 선택회로의 제2실시예이다.2 is a second embodiment of a clock signal selection circuit according to the present invention.

Claims (1)

각각이 상이한 클럭속도를 가지는 2이상의 클럭을 갖추고 있는 장치에 있어서, 외부로부터 수신된 클럭선택 신호를 저장하는 레지스터, 상기 레지스터로부터의 클럭선택신호를 출력을 디코딩하기 위한 디코더, 상기 클럭의 출력단자에 접속되며 상기 디코더의 출력단자에 각각 접속되는 버퍼수단을 포함하는 것을 특징으로 하는 클럭신호 선택회로.2. An apparatus having two or more clocks, each having a different clock rate, comprising: a register for storing a clock selection signal received from an external device; a decoder for decoding a clock selection signal from the register; and an output terminal of the clock. And a buffer means connected to each of the output terminals of the decoder. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920003642A 1992-03-05 1992-03-05 Clock signal selection circuit KR930020843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920003642A KR930020843A (en) 1992-03-05 1992-03-05 Clock signal selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920003642A KR930020843A (en) 1992-03-05 1992-03-05 Clock signal selection circuit

Publications (1)

Publication Number Publication Date
KR930020843A true KR930020843A (en) 1993-10-20

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ID=67257244

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920003642A KR930020843A (en) 1992-03-05 1992-03-05 Clock signal selection circuit

Country Status (1)

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KR (1) KR930020843A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100238717B1 (en) * 1993-10-13 2000-01-15 가와까미게에 Cosmetic material container

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100238717B1 (en) * 1993-10-13 2000-01-15 가와까미게에 Cosmetic material container

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