KR860700300A - Input memory circuit means and its distribution method - Google Patents

Input memory circuit means and its distribution method

Info

Publication number
KR860700300A
KR860700300A KR1019860700311A KR860700311A KR860700300A KR 860700300 A KR860700300 A KR 860700300A KR 1019860700311 A KR1019860700311 A KR 1019860700311A KR 860700311 A KR860700311 A KR 860700311A KR 860700300 A KR860700300 A KR 860700300A
Authority
KR
South Korea
Prior art keywords
input
output
data bus
storage means
coupled
Prior art date
Application number
KR1019860700311A
Other languages
Korean (ko)
Inventor
리 클로커 케빈
Original Assignee
빈센트 죠셉로너
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 빈센트 죠셉로너, 모토로라 인코포레이티드 filed Critical 빈센트 죠셉로너
Publication of KR860700300A publication Critical patent/KR860700300A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3856—Operand swapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow
    • G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Programmable Controllers (AREA)

Abstract

내용 없음No content

Description

입력 기억 회로 수단 및 그 분배 사용방법Input memory circuit means and its distribution method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 제2도의 디지탈 신호 처리기의 다른 실시예의 블록선도.3 is a block diagram of another embodiment of the digital signal processor of FIG.

Claims (5)

데이타 버스를 통해 외부 회로로부터 연산 논리 장치(ALU)에 결합되어지는 입력 피연산자를 수신하는 데이타 처리기내에서 연산 논리 장치 및 데이타 버스에 의해 분배 이용하도록 피연산자를 기억하는 회로 수단으로서, 제1입력 단자, 제1출력 단자 및 제2출력 단자를 갖는 입력 기억 수단을 구비하며, 상기 제1입력 단자는 데이타 버스에 결합되어 입력피연산자를 선택적으로 수신하고, 상기 제1출력 단자는 연산 논리 장치에 결합되어 상기 입력 기억 수단의 출력을 연산 논리 장치에 선택적으로 결합하고, 상기 제2출력 수단은 입력단자에 결합에 되어 상기 입력 기억 수단의 출력을 상기 데이타 버스에 선택적으로 궤환 결합하는 것을 특징으로 하는 입력 기억회로 수단.A circuit means for storing an operand for distribution by an arithmetic logic device and a data bus in a data processor that receives an input operand coupled to an arithmetic logic unit (ALU) from an external circuit via a data bus, comprising: a first input terminal, Input storage means having a first output terminal and a second output terminal, said first input terminal being coupled to a data bus to selectively receive an input operand, said first output terminal being coupled to an arithmetic logic device to And selectively coupling the output of the input storage means to the arithmetic logic device, wherein the second output means is coupled to an input terminal to selectively feedback-couple the output of the input storage means to the data bus. Way. 제1항에 있어서, 또한 제2출력 단자에 결합된 입력 및 입력 단자에 결합된 출력을 가져 상기 입력 기억 수단의 출력을 상기 데이타 버스상으로 선택적으로 구동하는 데이타 버스 구동기 수단을 구비하는 것을 특징으로 하는 입력 기억회로 수단.2. The apparatus of claim 1, further comprising data bus driver means having an input coupled to a second output terminal and an output coupled to an input terminal to selectively drive the output of the input storage means onto the data bus. Input memory circuit means. 제1항에 있어서, 또한 입력 단자에 결합된 제1입력과, 연산 논리 장치의 출력에 결합되어 데이타 버스로부터의 피연산자나 또는 연산 논리 장치의 출력을 입력 기억 수단에 선택적으로 결합하는 제2입력을 구비하는 것을 특징으로 하는 입력 기억회로 수단.2. The apparatus of claim 1, further comprising a first input coupled to the input terminal and a second input coupled to the output of the arithmetic logic unit to selectively couple an operand from a data bus or an output of the arithmetic logic unit to the input storage means. And an input memory circuit means. 연산 논리 장치와 데이타 버스간에서 데이타 처리기의 입력 기억 수단에 대한 분배 사용의 방법으로서, 데이타 버스로부터의 입력 피연산자를 입력 기억 수단에 선택적으로 결합하는 단계와, 입력 기억 수단의 출력을 연산 논리 장치에 선택적으로 결합하고, 한편으로는 입력 기억 수단의 출력을 데이타 버스에 선택적으로 제한 결합하는 단계를 구비하는 것을 특징으로 하는 입력 기억회로 수단의 분배 사용방법.A method of distributing use of an input storage means of a data processor between an operational logic device and a data bus, comprising: selectively coupling an input operand from the data bus to an input storage means, and outputting the input storage means to the operational logic device. Selectively coupling and, on the one hand, selectively restricting coupling the output of the input storage means to the data bus. 제4항에 있어서, 또한 입력 기억 수단의 출력을 데이타 버스에 결합하기 전에 연산 논리 장치의 출력을 입력 기억 수단에 선택적으로 기억하는 단계를 구비하는 것을 특징으로 하는 입력 기억회로 수단의 분배 사용방법.5. The method of claim 4, further comprising the step of selectively storing the output of the arithmetic logic unit in the input storage means before coupling the output of the input storage means to the data bus. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019860700311A 1984-09-28 1985-07-26 Input memory circuit means and its distribution method KR860700300A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US65559984A 1984-09-28 1984-09-28
US65528584A 1984-09-28 1984-09-28
US655599 1984-09-28
US655285 1984-09-28
PCT/US1985/001423 WO1986002181A1 (en) 1984-09-28 1985-07-26 A digital signal processor for single cycle multiply/accumulation

Publications (1)

Publication Number Publication Date
KR860700300A true KR860700300A (en) 1986-08-01

Family

ID=27096944

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860700311A KR860700300A (en) 1984-09-28 1985-07-26 Input memory circuit means and its distribution method

Country Status (3)

Country Link
EP (1) EP0197945A1 (en)
KR (1) KR860700300A (en)
WO (1) WO1986002181A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809212A (en) * 1985-06-19 1989-02-28 Advanced Micro Devices, Inc. High throughput extended-precision multiplier
JPS6211933A (en) * 1985-07-09 1987-01-20 Nec Corp Arithmetic circuit
US4754421A (en) * 1985-09-06 1988-06-28 Texas Instruments Incorporated Multiple precision multiplication device
US4999802A (en) * 1989-01-13 1991-03-12 International Business Machines Corporation Floating point arithmetic two cycle data flow
JPH04302522A (en) * 1991-03-29 1992-10-26 Hitachi Ltd Arithmetic circuit, and adaptive filter and echo canceler using same
KR940010241B1 (en) * 1991-12-14 1994-10-22 산성전자 주식회사 Motion vector detecting method
GB2317978B (en) * 1994-03-02 1998-05-20 Advanced Risc Mach Ltd Electronic multiplying and adding apparatus and method
GB2291515B (en) * 1994-07-14 1998-11-18 Advanced Risc Mach Ltd Data processing using multiply-accumulate instructions
DE19637369C2 (en) * 1996-09-13 2001-11-15 Micronas Gmbh Digital signal processor with multiplier and method
GB2321979B (en) * 1997-01-30 2002-11-13 Motorola Ltd Modular multiplication circuit
US5933797A (en) * 1997-02-28 1999-08-03 Telefonaktiebolaget Lm Ericsson (Publ) Adaptive dual filter echo cancellation
EP1058185A1 (en) * 1999-05-31 2000-12-06 Motorola, Inc. A multiply and accumulate apparatus and a method thereof
EP3835938A1 (en) * 2019-12-11 2021-06-16 Unify Patente GmbH & Co. KG Computer-implemented method of executing an arithmetic or logic operation in combination with an accumulate operation and processor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761698A (en) * 1972-04-24 1973-09-25 Texas Instruments Inc Combined digital multiplication summation
US4025771A (en) * 1974-03-25 1977-05-24 Hughes Aircraft Company Pipe line high speed signal processor
US4041461A (en) * 1975-07-25 1977-08-09 International Business Machines Corporation Signal analyzer system
US4339793A (en) * 1976-12-27 1982-07-13 International Business Machines Corporation Function integrated, shared ALU processor apparatus and method
US4194241A (en) * 1977-07-08 1980-03-18 Xerox Corporation Bit manipulation circuitry in a microprocessor
US4130879A (en) * 1977-07-15 1978-12-19 Honeywell Information Systems Inc. Apparatus for performing floating point arithmetic operations using submultiple storage
FR2413712A1 (en) * 1977-12-30 1979-07-27 Ibm France SPECIALIZED MICROPROCESSOR FOR CALCULATING THE SUM OF PRODUCTS OF TWO COMPLEX OPERANDS
US4215416A (en) * 1978-03-22 1980-07-29 Trw Inc. Integrated multiplier-accumulator circuit with preloadable accumulator register

Also Published As

Publication number Publication date
EP0197945A1 (en) 1986-10-22
WO1986002181A1 (en) 1986-04-10

Similar Documents

Publication Publication Date Title
KR860006743A (en) Data processing systems
KR950033803A (en) Multiple bit shift device, data processor using same, and multiple bit shift method
KR890008677A (en) Digital Multiplier Circuits and Digital Multiplier-Accumulator Circuits
KR870005316A (en) Information data output device of power system
KR860700300A (en) Input memory circuit means and its distribution method
KR870004569A (en) Automatic gain control device
JPS54122043A (en) Electronic computer
KR840001410A (en) Programmable Logic Units
KR850006802A (en) Data transmission device
KR890015119A (en) Data processor
KR860004360A (en) Microprocessor Interface Device for Telecommunication System
KR920006870A (en) Data processing device
JPS5510614A (en) Controller
JPS56118165A (en) Processor of video information
KR880006583A (en) Automotive microcomputer application control device
JPS57200985A (en) Buffer memory device
KR880009300A (en) Arithmetic processing unit
JPS56101247A (en) Audio output device
JPS56114026A (en) Data processor
KR930020843A (en) Clock signal selection circuit
KR940004446A (en) Bus interface device
KR970012172A (en) BUS CONTROLLER DEVICE FOR MULTI-Microprocessors
KR900018835A (en) One-way communication relay method between processors
JPS5576422A (en) Terminal unit
KR890017912A (en) Pseudo-DMA transmitter

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid