KR910012919A - Main CPU Supervisor - Google Patents

Main CPU Supervisor Download PDF

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Publication number
KR910012919A
KR910012919A KR1019890020567A KR890020567A KR910012919A KR 910012919 A KR910012919 A KR 910012919A KR 1019890020567 A KR1019890020567 A KR 1019890020567A KR 890020567 A KR890020567 A KR 890020567A KR 910012919 A KR910012919 A KR 910012919A
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KR
South Korea
Prior art keywords
main cpu
cpu
supervisory
buffer means
cpus
Prior art date
Application number
KR1019890020567A
Other languages
Korean (ko)
Other versions
KR930001793B1 (en
Inventor
홍재환
송광석
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR8920567A priority Critical patent/KR930001793B1/en
Publication of KR910012919A publication Critical patent/KR910012919A/en
Application granted granted Critical
Publication of KR930001793B1 publication Critical patent/KR930001793B1/en

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  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

내용 없음.No content.

Description

주(main) CPU 감시장치Main CPU Supervisor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 전체 블럭구성도.1 is an overall block diagram of the present invention.

Claims (1)

전전자 교환기의 주 CPU 보드(Board)에 있어서, CPU의 외부제어 신호들을 동기시켜 출력하는 동기버퍼수단(1), 상기 동기버퍼 수단(1)에 연결된 주 CPU(2)와 감시 CPU(4), 상기 주 CPU(2)와 감시 CPU(4)에 연결되어 두 CPU(2,4)의 공통 AS 신호를 출력해내는 동기회로수단(3), 상기 주 CPU(2)와 감시 CPU(4)의 데이타 입출력단에 연결하여 주 CPU(2)에 입력되는 데이타만을 감시 CPU(4)로 제공하는 데이타 버퍼수단(6), 상기 주 CPU(2)와 감시 CPU(4)에 연결되어 두 CPU(2,4)의 어드레스 수개를 각각 취한후 비교결과를 출력하는 주 CPU(2)의 감시운용을 신속하게 전달하는 비교 수단(5)으로 구성된 것을 특징으로 하는 주 CPU 감시장치.In the main CPU board (Board) of the electronic switchboard, a synchronization buffer means (1) for synchronizing and outputting external control signals of the CPU, the main CPU (2) and the monitoring CPU (4) connected to the synchronization buffer means (1). Synchronous circuit means (3) connected to the main CPU (2) and the supervisory CPU (4) to output a common AS signal of the two CPUs (2, 4), the main CPU (2) and the supervisory CPU (4) A data buffer means 6 connected to the data input / output terminal of the main CPU 2 to provide only the data inputted to the main CPU 2 to the supervisory CPU 4, and the two CPUs connected to the main CPU 2 and the supervisory CPU 4; And a comparing means (5) which quickly transmits the monitoring operation of the main CPU (2) which outputs the comparison result after taking several addresses of 2 and 4, respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8920567A 1989-12-30 1989-12-30 Main-c.p.u. watching apparatus KR930001793B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR8920567A KR930001793B1 (en) 1989-12-30 1989-12-30 Main-c.p.u. watching apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR8920567A KR930001793B1 (en) 1989-12-30 1989-12-30 Main-c.p.u. watching apparatus

Publications (2)

Publication Number Publication Date
KR910012919A true KR910012919A (en) 1991-08-08
KR930001793B1 KR930001793B1 (en) 1993-03-13

Family

ID=19294611

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8920567A KR930001793B1 (en) 1989-12-30 1989-12-30 Main-c.p.u. watching apparatus

Country Status (1)

Country Link
KR (1) KR930001793B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236099A1 (en) * 1992-05-06 1993-11-11 Samsung Electronics Co Ltd Column redundant circuit for a semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4236099A1 (en) * 1992-05-06 1993-11-11 Samsung Electronics Co Ltd Column redundant circuit for a semiconductor memory device
DE4236099C2 (en) * 1992-05-06 2001-01-11 Samsung Electronics Co Ltd Redundancy column circuit for a semiconductor memory device

Also Published As

Publication number Publication date
KR930001793B1 (en) 1993-03-13

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