KR890015530A - Parallel Data Communication Control Circuit in Redundant Processor - Google Patents

Parallel Data Communication Control Circuit in Redundant Processor Download PDF

Info

Publication number
KR890015530A
KR890015530A KR1019880003051A KR880003051A KR890015530A KR 890015530 A KR890015530 A KR 890015530A KR 1019880003051 A KR1019880003051 A KR 1019880003051A KR 880003051 A KR880003051 A KR 880003051A KR 890015530 A KR890015530 A KR 890015530A
Authority
KR
South Korea
Prior art keywords
control circuit
parallel data
data communication
communication control
processors
Prior art date
Application number
KR1019880003051A
Other languages
Korean (ko)
Inventor
최병철
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019880003051A priority Critical patent/KR890015530A/en
Publication of KR890015530A publication Critical patent/KR890015530A/en

Links

Landscapes

  • Hardware Redundancy (AREA)

Abstract

내용 없음No content

Description

이중화 프로세서에 있어서 병렬 데이타 통신 제어회로Parallel Data Communication Control Circuit in Redundant Processor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 3 도는 본 발명에 따른 블럭도.3 is a block diagram according to the present invention.

Claims (1)

이중화된 제 1,2프로세서(10,20)를 구비한 병렬데이타 통신 제어회로에 있어서, 이중화되어 액티브 또는 대기 상태로 있으면서 위급할때 대기상태에 있는 프로세서에 의해 처리하던 모든 작업을 받아 계속 실행하는 제 1,2프로세서(10,20)와, X-버스상의 병렬데이터를 입출력하며 핸드세이크 제어신호를 출력하는 병렬 입출력 제어회로(50,60)와, 상기 병렬 입출력 제어회로(50,60)의 핸드세이크 제어신호를 인터럽트 요구신호로 받아들이어 상기 제 1,2프로세서(10,20)의 인터럽트 신호를 발생하는 프로그램어블 인터럽트제어회로(30,40)로 구성됨을 특징으로 하는 회로.In a parallel data communication control circuit having redundant first and second processors (10 and 20), the dual data processor is redundant and is in an active or standby state, and receives and continues to execute all the tasks processed by a processor in an emergency state in an emergency state. The first and second processors 10 and 20, parallel input / output control circuits 50 and 60 for inputting and outputting parallel data on the X-bus and outputting a handshake control signal, and the parallel input and output control circuits 50 and 60. And a programmable interrupt control circuit (30,40) for receiving a handshake control signal as an interrupt request signal and generating an interrupt signal for said first and second processors (10,20). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880003051A 1988-03-22 1988-03-22 Parallel Data Communication Control Circuit in Redundant Processor KR890015530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880003051A KR890015530A (en) 1988-03-22 1988-03-22 Parallel Data Communication Control Circuit in Redundant Processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880003051A KR890015530A (en) 1988-03-22 1988-03-22 Parallel Data Communication Control Circuit in Redundant Processor

Publications (1)

Publication Number Publication Date
KR890015530A true KR890015530A (en) 1989-10-30

Family

ID=68241251

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880003051A KR890015530A (en) 1988-03-22 1988-03-22 Parallel Data Communication Control Circuit in Redundant Processor

Country Status (1)

Country Link
KR (1) KR890015530A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100575608B1 (en) * 1998-10-09 2006-09-28 매그나칩 반도체 유한회사 Bus control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100575608B1 (en) * 1998-10-09 2006-09-28 매그나칩 반도체 유한회사 Bus control circuit

Similar Documents

Publication Publication Date Title
KR860004352A (en) I / O processing unit
KR910017307A (en) Neuro chip and neuro computer with the chip
KR850005116A (en) Data processing systems
KR970071218A (en) Serial communication port switching circuit
KR910003898A (en) Monolithic Integrated Circuit for Power
KR870010444A (en) Data processor
KR860700300A (en) Input memory circuit means and its distribution method
KR890015530A (en) Parallel Data Communication Control Circuit in Redundant Processor
KR830008221A (en) Numerical Control Device
KR910003475A (en) Sequence controller
KR890012219A (en) Keyboard selection method and device in computer system
JPS55108057A (en) Duplex control unit
KR920014037A (en) I / O equipment matching device of redundant processor system
SU1621143A1 (en) Ik-type flip-flop
KR970012172A (en) BUS CONTROLLER DEVICE FOR MULTI-Microprocessors
KR920015199A (en) Processor failure prevention system using redundant processor
KR920018566A (en) Information processing device
JPS6478360A (en) Information processor
KR900018835A (en) One-way communication relay method between processors
KR890008645A (en) Visual system control method and device
KR900004002A (en) Integrated circuit layout
KR830002282A (en) Bus connection system
KR920014317A (en) Space Switch Processor Redundancy Control Method in Electronic Switching System
KR900005757A (en) External music source power control device of exchange system
JPS5752934A (en) Electronic computer system

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination