KR900004002A - Integrated circuit layout - Google Patents

Integrated circuit layout Download PDF

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Publication number
KR900004002A
KR900004002A KR1019890011494A KR890011494A KR900004002A KR 900004002 A KR900004002 A KR 900004002A KR 1019890011494 A KR1019890011494 A KR 1019890011494A KR 890011494 A KR890011494 A KR 890011494A KR 900004002 A KR900004002 A KR 900004002A
Authority
KR
South Korea
Prior art keywords
block
integrated circuit
functional block
control
circuit layout
Prior art date
Application number
KR1019890011494A
Other languages
Korean (ko)
Other versions
KR920005864B1 (en
Inventor
츠네아키 구도
다케지 도쿠마루
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR900004002A publication Critical patent/KR900004002A/en
Application granted granted Critical
Publication of KR920005864B1 publication Critical patent/KR920005864B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

Abstract

내용 없음.No content.

Description

집적회로의 배치구조Integrated circuit layout

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 1실시예에 따른 집적회로의 배치구조를 도시해 놓은 도면,1 is a view showing an arrangement of an integrated circuit according to an embodiment of the present invention,

제3도는 제 1도 몇 제 2도에 도시된 배치구조의 배선의 레이아웃을 도시해 놓은 도면,FIG. 3 is a view showing the layout of the wiring of the arrangement structure shown in FIGS.

Claims (3)

입출력되는 데이터신호에 대해 소정의 처리를 행하는 기능블록(1)과, 이 기능블록(1)을 제어하기 위한 제어신호가 상기 기능블록(1)과의 사이에서 상기 데이터신호와 직교하는 방향으로 압출력되도록 상기 기능블록(1)을 제어하는 제어블록(3)을 구비하고, 상기 기능블록(1)이 사이에 삽입되도록 상기 제어블록(3)을 상기 기능블록(1)의 양측에 분산 배치해서 제어신호가 상기 기능블록(1)에 대해서 각각 다른 방향으로부터 입출력되도록 되어 있는 것을 특징으로 하는 집적회로의 배치구조.The function block 1 which performs a predetermined process with respect to the input / output data signal, and the control signal for controlling this function block 1 are pressed in the direction orthogonal to the said data signal between the said function block 1; And a control block 3 for controlling the functional block 1 to be output, and distributing the control block 3 on both sides of the functional block 1 so that the functional block 1 is interposed therebetween. An arrangement structure of an integrated circuit, characterized in that control signals are inputted and outputted from different directions with respect to the functional block (1). 제1항에 있어서, 상기 제어블록(3)과 상기 기능블록(1)의 사이에 상기 제어신호를 상기 기능블록(1)으로 입력시키는 버퍼회로(13)가 배치된 것을 특징으로 하는 집적회로의 배치구조.2. An integrated circuit according to claim 1, characterized in that a buffer circuit (13) is arranged between said control block (3) and said functional block (1) for inputting said control signal to said functional block (1). Layout structure. 제1항 또는 제2항에 있어서, 상기 제어블록(3)이 표준셀을 이용한 자동배치배선에 의해서 형성되는 것을 특징으로 하는 집적회로의 배치구조.An integrated circuit arrangement structure according to claim 1 or 2, characterized in that the control block (3) is formed by automatic arrangement wiring using a standard cell. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890011494A 1988-08-12 1989-08-12 Disposing structure for intergrated circuit KR920005864B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63200202A JP2790287B2 (en) 1988-08-12 1988-08-12 Integrated circuit layout structure
JP63-200202 1988-08-12

Publications (2)

Publication Number Publication Date
KR900004002A true KR900004002A (en) 1990-03-27
KR920005864B1 KR920005864B1 (en) 1992-07-23

Family

ID=16420499

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890011494A KR920005864B1 (en) 1988-08-12 1989-08-12 Disposing structure for intergrated circuit

Country Status (2)

Country Link
JP (1) JP2790287B2 (en)
KR (1) KR920005864B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9231895B2 (en) 2012-10-23 2016-01-05 International Business Machines Corporation Tag management of information technology services improvement
JP6384201B2 (en) 2014-08-28 2018-09-05 セイコーエプソン株式会社 Integrated circuit device and electronic apparatus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56134745A (en) * 1980-03-26 1981-10-21 Nec Corp Integrated circuit device
JPS59127845A (en) * 1983-01-13 1984-07-23 Seiko Epson Corp Test circuit for integrated circuit
JPS59149424A (en) * 1983-02-15 1984-08-27 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH0682801B2 (en) * 1983-12-23 1994-10-19 株式会社日立製作所 Semiconductor memory device and layout method thereof
JPS6244835A (en) * 1985-08-23 1987-02-26 Hitachi Ltd Microprocessor

Also Published As

Publication number Publication date
JP2790287B2 (en) 1998-08-27
JPH0250459A (en) 1990-02-20
KR920005864B1 (en) 1992-07-23

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