KR960043212A - Semiconductor memory device and circuit arrangement method with improved input characteristics - Google Patents

Semiconductor memory device and circuit arrangement method with improved input characteristics Download PDF

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Publication number
KR960043212A
KR960043212A KR1019950013270A KR19950013270A KR960043212A KR 960043212 A KR960043212 A KR 960043212A KR 1019950013270 A KR1019950013270 A KR 1019950013270A KR 19950013270 A KR19950013270 A KR 19950013270A KR 960043212 A KR960043212 A KR 960043212A
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KR
South Korea
Prior art keywords
memory device
semiconductor memory
pads
input buffers
main control
Prior art date
Application number
KR1019950013270A
Other languages
Korean (ko)
Other versions
KR0145220B1 (en
Inventor
장현순
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950013270A priority Critical patent/KR0145220B1/en
Priority to JP12529396A priority patent/JPH0922990A/en
Publication of KR960043212A publication Critical patent/KR960043212A/en
Application granted granted Critical
Publication of KR0145220B1 publication Critical patent/KR0145220B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

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  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 메모리장치의 배치방법에 관한 것이다.The present invention relates to a method of disposing a semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래기술에 따른 센터패드형의 반도체 메모리장치는 매인컨트롤 회로블럭내에 입력버퍼들이 집중되어 있었다. 이에 따라상기 입력버퍼들과 패드들사이의 거리가 멀어 외부입력신호가 입력버퍼까지 걸리는 시간지연이 상당했었다. 이로 인해 핀커패시턴스가 커지게 되므로 입력 버퍼들의 응답속도가 느리게 되어 고속동작에 상당히 불리 하였다.In the center pad semiconductor memory device according to the prior art, the input buffers are concentrated in the main control circuit block. As a result, the distance between the input buffers and the pads is so great that the time delay for the external input signal to reach the input buffer was considerable. As a result, the pin capacitance is increased, which slows the response speed of the input buffers, which is disadvantageous for high speed operation.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

상기의 문제점을 해결하기 위하여 본 발명에서는 입력버퍼들과 패드들과의 거리를 최소화되도록 상기 입력버퍼들을 매인컨트롤회로블럭과 패드들사이사이에 배치하였다.In order to solve the above problems, in the present invention, the input buffers are disposed between the main control circuit block and the pads to minimize the distance between the input buffers and the pads.

4. 발명의 중요한 용도4. Important uses of the invention

상술한 바와 같이 입력 버퍼들과 패드들과의 거리를 최소화하므로써 상기 입력버퍼들의 응답속도가 빨라지므로 대역폭이향상되어 고속동작에 탁월한 효과를 지니는 반도체 메모리 장치가 구현된다.As described above, since the response speed of the input buffers is increased by minimizing the distance between the input buffers and the pads, a bandwidth is improved, and a semiconductor memory device having an excellent effect on high speed operation is realized.

Description

입력특성이 개선된 반도체 메모리장치 및 회로배치방법Semiconductor memory device and circuit arrangement method with improved input characteristics

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 실시예에 따른 반도체 메모리장치의 회로배치를 나타내는 배치도, 제4도는 본 발명의 실시예에 따른 반도체 메모리장치의 입력특성을 나타내는 파형도.3 is a layout view showing a circuit arrangement of a semiconductor memory device according to an embodiment of the present invention, and FIG. 4 is a waveform diagram showing input characteristics of a semiconductor memory device according to an embodiment of the present invention.

Claims (4)

패드들과 매인컨트롤회로블럭에 의해 분리된 서브메모리블럭들을 구비하는 반도체 메모리장치에 있어서,상기 매인 컨트롤회로블럭과 각각의 패드들사이에 배치된 입력버퍼들을 구비함을 특징으로 하는 반도체 메모리장치.A semiconductor memory device comprising pads and sub-memory blocks separated by a main control circuit block, the semiconductor memory device comprising input buffers disposed between the main control circuit block and respective pads. 제1항에 있어서 ,상기 패드들이 상기 서브메모리블럭들사이의 장변방향으로 칩중앙에 배치됨을 특징으로하는 반도체 메모리 장치.The semiconductor memory device of claim 1, wherein the pads are disposed at a chip center in a long side direction between the sub memory blocks. 패드들과 매인 컨트롤회로블럭에 의해 분리된 서브메모리블럭들을 구비하는 반도체 메모리장치의 배치방법에 있어서,상기 매인 컨트롤회로블럭과 각각의 패드들사이에 입력버퍼들을 배치하여 상기패드들과 입력버퍼들과의 거리를최소화함을 특징으로 하는 반도체 메모리장치의 배치방법.A method of arranging a semiconductor memory device having pads and sub-memory blocks separated by a main control circuit block, the method comprising: disposing input buffers between the main control circuit block and respective pads; A method of arranging a semiconductor memory device, characterized by minimizing the distance from the device. 제3항에 있어서, 상기 패드들이 상기 서브메모리블럭들 사이의 장변방향으로 칩중앙에 배치됨을 특징으로하는 반도체 메모리장치의 배치방법.4. The method of claim 3, wherein the pads are disposed at a chip center in a long side direction between the sub memory blocks. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950013270A 1995-05-25 1995-05-25 Semiconductor memory device and circuit arrangement method with improved input characteristics KR0145220B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950013270A KR0145220B1 (en) 1995-05-25 1995-05-25 Semiconductor memory device and circuit arrangement method with improved input characteristics
JP12529396A JPH0922990A (en) 1995-05-25 1996-05-21 Semiconductor memory with improved input characteristics and circuit arrangement method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950013270A KR0145220B1 (en) 1995-05-25 1995-05-25 Semiconductor memory device and circuit arrangement method with improved input characteristics

Publications (2)

Publication Number Publication Date
KR960043212A true KR960043212A (en) 1996-12-23
KR0145220B1 KR0145220B1 (en) 1998-07-01

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JP (1) JPH0922990A (en)
KR (1) KR0145220B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102611888B1 (en) * 2016-11-07 2023-12-11 삼성전자주식회사 Layout method for semiconductor device based on swiching activity and manufacturing
CN112435696A (en) 2019-08-26 2021-03-02 长鑫存储技术有限公司 Chip and electronic device

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Publication number Publication date
JPH0922990A (en) 1997-01-21
KR0145220B1 (en) 1998-07-01

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