JPH0922990A - Semiconductor memory with improved input characteristics and circuit arrangement method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of performing a high speed operation by securing a high band width. SOLUTION: In the semiconductor memory device having many pads and many input buffers corresponding to the pads, the many pads 16 and the buffers 14, 12,... are so alternately laid out as to form the pairs with the one pad and the one input pad adjacently corresponding thereto, thereby minimizing the distance between the pad and the buffer corresponding thereto.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of performing a high speed operation by adaptively operating to a high frequency input by minimizing a distance between a pad and an input buffer.

[0002]

2. Description of the Related Art Parameters indicating the performance of a semiconductor memory device, such as power consumption, high speed operation, and size, are closely related to the layout of circuits and elements in the semiconductor memory device. Therefore, as the degree of integration of the semiconductor memory device becomes higher, proper arrangement of circuits and elements inside the chip becomes more important issue. In the current semiconductor memory device, the system and the memory device are required to have higher functionality in order to improve the performance, and in particular, in order to improve the bandwidth, which is directly related to the high speed operation as described above. There is a tendency for various studies to become active. Examples of reflecting such a tendency are SDRAM (Synchronous DRAM) and SGR.
AM (Synchronous Graphic RAM), RDRAM (Rambus
New devices such as DRAM) and MDRAM (Mosys DRAM) are appearing one after another.

The common feature of these new memories is 100 MHz.
This means that it operates at a clock frequency of z or higher.
Due to such high frequency operation, the operating margin of the memory device in the system is further reduced. In order to realize a high-speed operation by ensuring a high bandwidth and enabling a high-frequency operation, it is necessary to reduce the setup / hold time of the input signal and the pin capacitance. Various methods have been applied in the aspects of system and memory device in order to reduce the setup / hold time of the input signal and reduce the pin capacitance.

FIG. 2 shows a circuit arrangement of a semiconductor memory device according to the prior art. In the figure, a rectangular chip 2 having a first area and serving as a semiconductor memory substrate
The rectangular first to fourth sub-memory blocks 4, 6, 8, 10 having a predetermined second area smaller than the first area.
Is formed. First and second sub-memory blocks 4,
6 are divided into upper and lower parts of the chip 2 with the pad 16 as a reference, and the first and second sub-memory blocks 4 and 6 form a first memory bank. Similarly, the third and fourth sub memory blocks 8 and 10 are also pad 1
The third and fourth sub memory blocks 8 and 10 are divided and arranged in the upper and lower parts of the chip 2 with reference to 6, and form a second memory bank. The first and second memory banks mainly include the main control circuit block 12 and the chip 2
Separately placed on both the left and right sides of the. Although a large number of peripheral circuits are arranged in the main control circuit block 12, the input buffer 14 is also included in the large number of peripheral circuits. The input signal line 18 connects between the pad 16 and the input buffer 14. An internal signal line 20 is connected to the output terminal of the input buffer 14.

As a reference, when the pad 16 is arranged in the center of the chip between the sub memory blocks as described above, it is called a center pad type and is used for this center pad type. The lead frame is called a LOC (Lead On Chip) type. The LOC type semiconductor memory device used in the center pad type has advantages of reducing power bumping and reducing the influence of α-particles.

FIG. 4 is a waveform diagram showing one of the input characteristics of the semiconductor memory device of FIG. In the semiconductor memory device configured as shown in FIG.
6 is transmitted to the input buffer 14 through the input signal line 18. Then, the input buffer 14 performs a predetermined buffering operation, and the output of the input buffer 14 is the internal signal line 20.
Is transmitted to the peripheral circuits in the main control circuit block 12 through.

Meanwhile, in the semiconductor memory device as shown in FIG. 2, the pad and the corresponding input buffer are far apart, so that it takes a long time to transmit the external input signal to the input buffer. Further, as shown in FIG. 4, the pin capacitance becomes large, so that the output time at the input buffer becomes long. Therefore, in the semiconductor memory device as shown in FIG. 2, it is difficult to shorten the setup / hold time of the input signal required for high speed operation, and it is difficult to secure a high bandwidth. Is a major obstacle to accomplishing.

[0008]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor memory device which secures a high bandwidth and can operate at high speed. Another object of the present invention is to provide a method of arranging a semiconductor memory device for ensuring a high bandwidth.

[0009]

In order to achieve such an object, the present invention comprises a main control circuit block and a large number of sub-memory blocks separately arranged on both sides of the main control circuit block. In a semiconductor memory device having a plurality of pads and a plurality of input buffers connected to the pads via input signal lines, the plurality of pads and the plurality of input buffers correspond to one pad and the pad. The input buffers are alternately arranged so as to be adjacent to each other to form a pair, and each of these input buffers is connected to the main control circuit block through a buffer output line. Characterize.

In order to achieve another object, the present invention provides
A main control circuit block, a large number of sub-memory blocks arranged on both sides of the main control circuit block as a center, a large number of pads, and a large number of input buffers connected to each of these pads through input signal lines. In the method for arranging a semiconductor memory device, the plurality of pads and the plurality of input buffers are alternately arranged so that one pad and one corresponding input buffer are adjacent to each other to form a pair. The arrangement is such that the distance between the pad and the input buffer corresponding to the pad is minimized.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 illustrates a circuit layout of a semiconductor memory device according to an exemplary embodiment of the present invention. In the figure, elements and circuits having the same configuration and operability as those of the semiconductor memory device of FIG. 1 are designated by the same reference numerals.

In FIG. 1, rectangular first to fourth rectangular areas each having a predetermined second area smaller than the first area are formed on a rectangular chip 2 having a first area and serving as a substrate of a semiconductor memory.
Sub memory blocks 4, 6, 8 and 10 are formed.
The first and second sub-memory blocks 4 and 6 are divided and arranged in respective upper and lower parts of the chip 2 with reference to the row of a large number of pads 16, 16, ... Arranged in a row. The sub-memory blocks 4 and 6 of 1 constitute a first memory bank. Similarly, the third and fourth sub memory blocks 8 and 10 also have a large number of pads 16 arranged in a line,
The third and fourth sub-memory blocks 8 and 10 are divided and arranged in the upper and lower parts of the chip 2 with the column of 16 ... As a reference, and form a second memory bank. Also the first
The second memory bank is separately arranged on the left and right sides of the chip 2 with the main control circuit block 12 as the center. A large number of peripheral circuits are arranged in the main control circuit block 12. And a large number of input buffers 14, 14, ...
One input buffer and one corresponding pad are arranged so as to be adjacent to each other to form a pair, and are alternately arranged on the pad arrangement row. The internal signal line 20 serving as a buffer output line of the input buffer 14 runs to many peripheral circuits forming the main control circuit block 12.

FIG. 3 is a waveform diagram showing the input characteristic of the semiconductor memory device according to the embodiment of the present invention. In the semiconductor memory device according to the present invention configured as described above, when an external input signal is input to the pad 16, the pad 16
Output of the input buffer 14 through the input signal line 18.
Is transmitted to Then, the input buffer 14 performs a predetermined buffering operation, and then the output of the input buffer 14 is transmitted to the peripheral circuit in the main control circuit block 12 through the internal signal line 20.

Here, by comparing FIG. 3 with FIG. 4, it can be clearly understood that the semiconductor memory device according to the embodiment of the present invention has further improved input characteristics as compared with the semiconductor memory device according to the prior art. . This will be described in more detail as follows.

The input level characteristic of a general semiconductor memory device, that is, Vih / Vil (Vih indicates the minimum logic "high" of the voltage in the input buffer, Vil indicates the maximum logic "low" of the voltage in the input buffer). , A voltage difference different from the value of (Vih + Vil) / 2 due to changes in supply voltage, temperature, length of input signal line, and the like. This is a known matter. 3 and 4, Vt (H) indicates a voltage level that the device actually recognizes as a logic "high", and Vt (L) indicates a voltage level that the device actually recognizes as a logic "low". The voltage levels of Vt (H) and Vt (L) in this embodiment are 1.
8 V and 1.0 V. Due to the change according to the characteristics of the input level as described above, the output time points between the input buffers become different. As a result, the setup / hold time margin is further reduced.

As shown in FIGS. 3 and 4, in the conventional semiconductor memory device, the output time "A1 + B1" between the input signal lines is 2 ns (10 ^-9 seconds). Output time between "A2 + B
2 ″ is 1 ns. From this, it can be seen that the input characteristics of the semiconductor memory device according to the present invention are improved as compared with the prior art. Further, the delay degree which actually affects the setup / hold time is (A1-α1). ) And (B1-
It will be reduced from (β1) to (A2-α2) and (B2-β2).

In this embodiment, setup /
The improvement of the hold time is 1ns, but the semiconductor memory that operates at high frequency, for example, SDR of 100MHz class or higher
AM has a setup / hold delay of 4 ns
In this case, a larger effect can be expected. That is, in the semiconductor memory device in which the clock cycle tends to be further shortened in the future, it can be expected to bring about an even greater effect. Further, according to the arrangement of the present invention, it is apparent that the length of the input signal line is significantly shortened and the pin capacitance is reduced, which is suitable for a semiconductor memory device for high speed operation.

[0018]

As described above, according to the present invention, it is possible to reduce the time delay of the output of the input buffer with respect to the external input signal, which makes it possible to secure a high bandwidth and to increase the speed of the semiconductor memory device. It can be expected to greatly improve operability.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit arrangement of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit arrangement of a semiconductor memory device according to a conventional technique.

FIG. 3 is a waveform diagram showing input characteristics of the semiconductor memory device according to the embodiment of the present invention.

FIG. 4 is a waveform diagram showing input characteristics of the semiconductor memory device of FIG.

[Explanation of symbols]

 2 ... Chip 4, 6, 8, 10, Sub memory block 12 ... Main control circuit block 14 ... Input buffer 16 ... Pad 18 ... Input signal line 20 ... Internal signal Line (buffer output line)

Claims (4)

[Claims] 1. A main control circuit block, a large number of sub-memory blocks separately arranged on both sides of the main control circuit block, a large number of pads, and an input signal line connected to each of these pads. In the semiconductor memory device having a plurality of input buffers, the plurality of pads and the plurality of input buffers are formed such that one pad and one corresponding input buffer are adjacent to each other to form a pair. A semiconductor memory device, wherein the input buffers are alternately arranged and each of the input buffers is connected to the main control circuit block through a buffer output line. 2. The semiconductor memory device according to claim 1, wherein the pads and the input buffers are arranged in a line, and the arranged lines are arranged horizontally in the center of the chip. 3. A main control circuit block, a large number of sub-memory blocks separately arranged on both sides of the main control circuit block, a large number of pads, and an input signal line connected to each of these pads. In a method of arranging a semiconductor memory device including a plurality of input buffers, one pad and one corresponding input buffer are adjacent to each other to form a pair. By arranging the pads alternately, the distance between the pad and the corresponding input buffer is minimized. 4. The arrangement method according to claim 3, wherein the pads and the input buffers are arranged in a line, and the arrangement lines are arranged horizontally in the center of the chip.