KR970017687A

KR970017687A - Semiconductor memory device with shared page buffer

Info

Publication number: KR970017687A
Application number: KR1019950031477A
Authority: KR
Inventors: 김경래; 조성희
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-09-23
Filing date: 1995-09-23
Publication date: 1997-04-30

Abstract

본 발명은 반도체 메모리 장치에 관한 것으로, 특히 비트라인 선택신호에 응답하는 제1선택트랜지스터와, 접지라인 선택신호에 응답하는 제2선택 트랜지스터와, 제1 및 제2선택트랜지스터들의 사이에 연결된 복수의 셀트랜지스터들로 구성되고 비트라인 선택신호와 접지라인 선택신호에 의해 하나의 비트라인에 연결되는 N개의 셀스트링들; 비트라인 프리차지신호에 응답하는 비트라인 프리차지수단 및 비트라인에 전개된 셀데이타에 응답하는 스위칭 트랜지스터와, 프리세트신호에 응답하는 프리세트수단과, 클리어신호에 응답하는 클리어수단과, 클리어수단에 의해 클리어되고 상기 스위칭 트랜지스터를 통하여 프리세스수단의 상태에 따라 셀데이타를 래치하는 래치수단을 가지는 복수의 페이지 버퍼들로 이루어지고, 접지라인 선택신호에 의해 2N개의 셀스트링들이 동시 지정되고, 프리세트신호 및 클리어신호에 의해 2개의 페이지버퍼들이 동시에 지정되는 M개의 단위 셀어레이들 및 M개의 단위 셀어레이들의 각 페이지 버퍼들에 래치된 데이타를 M비트의 컬럼선택신호에 응답하여 멀티플렉싱하는 멀티플렉서를 구비한다. 따라서 본 발명에서는 페이지버퍼를 공유함으로써 회로구성을 간단하게 할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a first selection transistor in response to a bit line selection signal, a second selection transistor in response to a ground line selection signal, and a plurality of first and second selection transistors. N cell strings composed of cell transistors and connected to one bit line by a bit line selection signal and a ground line selection signal; Bit line precharge means for responding to the bit line precharge signal, switching transistors for responding to cell data developed on the bit line, preset means for responding to the preset signal, clearing means for responding to the clear signal, and clearing means And a plurality of page buffers having latch means for latching cell data according to the state of the access means through the switching transistor, and 2N cell strings are simultaneously designated by a ground line selection signal, and A multiplexer that multiplexes the data latched in the page buffers of the M unit cell arrays and the M unit cell arrays in which two page buffers are simultaneously designated by the set signal and the clear signal in response to an M-bit column selection signal. Equipped. Therefore, in the present invention, the circuit configuration can be simplified by sharing the page buffer.

Description

Semiconductor memory device with shared page buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 공유 페이지 버퍼를 가진 반도체 메모리 장치의 회로구성도,3 is a circuit diagram of a semiconductor memory device having a shared page buffer according to the present invention;

제4도는 제3도의 회로 동작을 설명하기 위한 타이밍도.4 is a timing diagram for explaining the circuit operation of FIG.

Claims

A first selection transistor in response to a corresponding bit line selection signal among the N bit line selection signals, a second selection transistor in response to a ground line selection signal, and a plurality of first connection transistors connected between the first and second selection transistors; N cell strings connected to one bit line by the bit line selection signal and the ground line selection signal composed of cell transistors, bit line precharge means in response to a bit line precharge signal, and the bit lines. A switching transistor responsive to cell data, a preset means responsive to a preset signal, a clearing means responsive to a clear signal, and cleared by said clearing means and according to the state of a preset means through said switching transistor. A plurality of page buffers having latch means for latching Data latched in each page buffer of M unit thin arrays and M unit cell arrays in which 2N cell strings are simultaneously designated by a signal, and two page buffers are simultaneously designated by the preset and clear signals. And a multiplexer for multiplexing in response to an M-bit column selection signal.

※ Note: The disclosure is based on the initial application.