KR920014037A - I / O equipment matching device of redundant processor system - Google Patents

I / O equipment matching device of redundant processor system Download PDF

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Publication number
KR920014037A
KR920014037A KR1019900022888A KR900022888A KR920014037A KR 920014037 A KR920014037 A KR 920014037A KR 1019900022888 A KR1019900022888 A KR 1019900022888A KR 900022888 A KR900022888 A KR 900022888A KR 920014037 A KR920014037 A KR 920014037A
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KR
South Korea
Prior art keywords
cpu
input
output
matching device
control means
Prior art date
Application number
KR1019900022888A
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Korean (ko)
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KR930011203B1 (en
Inventor
최영복
여환근
이충근
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019900022888A priority Critical patent/KR930011203B1/en
Publication of KR920014037A publication Critical patent/KR920014037A/en
Application granted granted Critical
Publication of KR930011203B1 publication Critical patent/KR930011203B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Hardware Redundancy (AREA)

Abstract

내용 없음No content

Description

이중화 프로세서 시스팀의 입출력 장비 정합장치I / O equipment matching device of redundant processor system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 이중화 프로세서 시스팀의 구성을 나타낸 블럭도, 제2도는 본 발명에 의한 입출력 정합장치의 구성을 나타낸 블럭도.1 is a block diagram showing a configuration of a redundant processor system to which the present invention is applied, and FIG. 2 is a block diagram showing a configuration of an input / output matching device according to the present invention.

Claims (3)

컴퓨터 시스템에서 맨-머신 통신을 위하여 입출력 장비와 시스템과의 입출력 정합을 위한 이중화 프로세서 시스템의 입출력 정합장치에 있어서; CPU(Central processing Unit)(41), 상기 CPU(41)에 연결되어 인터럽트를 발생하는 레지스터 수단(42), 상기 CPU(41)에 연결되어 입출력 데이터를 저장하는 이중 포트메모리(43), 상기 CPU(41)에 연결되어 프로그램을 저장하는 ROM(44), 상기 CPU(41)에 연결된 RAM(45), 상기 CPU(41)에 연결되어 입출력 장비와 정합하는 입출력 장비 제어수단(SCC:46), 상기 CPU(41)와 레지스터 수단(42)와 입출력 장비 제어수단(46)에 연결되어 상기 레지스터 수단(42) 및 입출력 장비 제어수단(46)에 의한 인터럽트를 상기 CPU(41)로 전달하는 인터럽트 처리수단(47), 및 상기 CPU(41)에 연결되어 상기 CPU(41)의 제어에 따라 포트 스위칭 제어신호를 출력하는 포트 스위칭 이중화 제어수단(48)으로 구성되는 것을 특징으로 하는 입출력 정합장치.An input / output matching device of a redundant processor system for input / output matching between an input / output device and a system for man-machine communication in a computer system; Central processing unit (CPU) 41, register means 42 connected to the CPU 41 to generate an interrupt, dual port memory 43 connected to the CPU 41 to store input / output data, and the CPU A ROM 44 connected to the 41 to store a program; a RAM 45 connected to the CPU 41; an input / output device control means (SCC) 46 connected to the CPU 41 to match the input / output device; Interrupt processing connected to the CPU 41, the register means 42, and the input / output equipment control means 46 to transfer interrupts by the register means 42 and the input / output equipment control means 46 to the CPU 41. Means (47), and port switching redundancy control means (48) connected to said CPU (41) for outputting a port switching control signal under control of said CPU (41). 제1항에 있어서, 상기 RAM(45)은 프로그램 수행시 버퍼의 역할을 하는 것을 특징으로 하는 입출력 정합장치.The input / output matching device according to claim 1, wherein the RAM (45) serves as a buffer when a program is executed. 제1항에 있어서, 상기 레지스터수단(42)은 동작상태 및 인터럽트 비트가 세트되는 것을 특징으로 하는 입출력 정합장치.The input / output matching device according to claim 1, wherein the register means (42) is set with an operating state and an interrupt bit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900022888A 1990-12-31 1990-12-31 Dual processor system KR930011203B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022888A KR930011203B1 (en) 1990-12-31 1990-12-31 Dual processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022888A KR930011203B1 (en) 1990-12-31 1990-12-31 Dual processor system

Publications (2)

Publication Number Publication Date
KR920014037A true KR920014037A (en) 1992-07-30
KR930011203B1 KR930011203B1 (en) 1993-11-25

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Application Number Title Priority Date Filing Date
KR1019900022888A KR930011203B1 (en) 1990-12-31 1990-12-31 Dual processor system

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KR (1) KR930011203B1 (en)

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KR930011203B1 (en) 1993-11-25

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