KR920013130A - I / O Processor Using Data Buffer RAM - Google Patents

I / O Processor Using Data Buffer RAM Download PDF

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Publication number
KR920013130A
KR920013130A KR1019900021867A KR900021867A KR920013130A KR 920013130 A KR920013130 A KR 920013130A KR 1019900021867 A KR1019900021867 A KR 1019900021867A KR 900021867 A KR900021867 A KR 900021867A KR 920013130 A KR920013130 A KR 920013130A
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KR
South Korea
Prior art keywords
data
buffer ram
data buffer
main memory
signal
Prior art date
Application number
KR1019900021867A
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Korean (ko)
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KR920010971B1 (en
Inventor
구교선
김중배
김길호
안대영
설대학
채미옥
안희일
윤석환
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019900021867A priority Critical patent/KR920010971B1/en
Publication of KR920013130A publication Critical patent/KR920013130A/en
Application granted granted Critical
Publication of KR920010971B1 publication Critical patent/KR920010971B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

내용 없음No content

Description

데이타 버퍼램을 이용한 입출력 처리기I / O Processor Using Data Buffer RAM

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 회로도, 제2도는 본 발명의 동작을 나타내는 플로챠트.1 is a circuit diagram of the present invention, Figure 2 is a flow chart showing the operation of the present invention.

Claims (1)

중앙처리기로 부터 데이타 버퍼램(4)을 지니고 있는 입출력 처리기의 중앙처리 디바이스(1)로 입출력 요구가 있으면 입출력 버스의 중재기에 입출력 버스 사용요청신호를 출력하는 단계와, 입출력 버스 사용허가신호가 입력되면 명령을 입출력 장치 제어기로 전하는 단계와, 입출력 장치의 내용을 기억장치에 일시저장한 후 데이타 버퍼램 이용요청신호를 중앙처리 디바이스(1)로 전달하는 단계와, 중앙처리 디바이스(1)로 부터 데이타 버퍼램 사용허가신호를 받으면 데이타를 데이타 버퍼램(4)으로 이동하여 전송이 완료되면 인터럽트를 출력하는 단계와 인터럽트를 받은 중앙처리 디바이스(1)가 주기억장치(1)로 어드레스 버스 요청신호를 출력하는 단계와, 주기억장치로 부터 어드레스 버스 허가신호가 접수되면 주기억장치로 데이타를 전송하는 단계와, 데이타를 전송받은 주기억장치에서 제어신호를 중앙처리 디바이스(1)로 전달하는 단계들에 의해 입출력처리를 수행하도록 한 데이타 버퍼램을 이용한 입출력 처리기.If there is an I / O request from the CPU to the CPU 1 of the I / O processor having the data buffer RAM 4, the I / O bus request signal is sent to the I / O bus arbiter. Outputting an input / output bus permission signal Is inputted, the command is transmitted to the I / O device controller, and the contents of the I / O device are temporarily stored in the memory device and then the data buffer RAM use request signal To the central processing device (1), and the data buffer RAM permission signal from the central processing device (1) Receives data and moves data to data buffer RAM (4). Interrupt when transfer is completed. Outputting steps and interrupts The CPU 1 receives the address bus request signal to the main memory 1; Outputting an address bus signal from the main memory; And receiving data, and transmitting the data to the main memory device, and transmitting the control signal to the central processing device (1) in the main memory device receiving the data. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900021867A 1990-12-26 1990-12-26 Input and output processor using data buffer ram KR920010971B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021867A KR920010971B1 (en) 1990-12-26 1990-12-26 Input and output processor using data buffer ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021867A KR920010971B1 (en) 1990-12-26 1990-12-26 Input and output processor using data buffer ram

Publications (2)

Publication Number Publication Date
KR920013130A true KR920013130A (en) 1992-07-28
KR920010971B1 KR920010971B1 (en) 1992-12-26

Family

ID=19308548

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021867A KR920010971B1 (en) 1990-12-26 1990-12-26 Input and output processor using data buffer ram

Country Status (1)

Country Link
KR (1) KR920010971B1 (en)

Also Published As

Publication number Publication date
KR920010971B1 (en) 1992-12-26

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