KR910012939A - Local Bus Control Subunit - Google Patents

Local Bus Control Subunit Download PDF

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Publication number
KR910012939A
KR910012939A KR1019890019505A KR890019505A KR910012939A KR 910012939 A KR910012939 A KR 910012939A KR 1019890019505 A KR1019890019505 A KR 1019890019505A KR 890019505 A KR890019505 A KR 890019505A KR 910012939 A KR910012939 A KR 910012939A
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KR
South Korea
Prior art keywords
local
bus control
control subunit
decoder
local bus
Prior art date
Application number
KR1019890019505A
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Korean (ko)
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KR920002667B1 (en
Inventor
이규호
이장선
Original Assignee
경상현
재단법인 한국전자통신 연구소
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Priority to KR1019890019505A priority Critical patent/KR920002667B1/en
Publication of KR910012939A publication Critical patent/KR910012939A/en
Application granted granted Critical
Publication of KR920002667B1 publication Critical patent/KR920002667B1/en

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  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

내용 없음.No content.

Description

로컬 버스 콘트롤 서브 유니트Local Bus Control Subunit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 블럭 구성도.1 is a block diagram of the present invention.

제2도의 (가), (나)는 본 발명의 어드레스 및 데이타 래치의 콘트롤 신호들을 나타낸 개략도.2A and 2B are schematic diagrams showing control signals of an address and data latch of the present invention.

제3도는 본 발명의 어드레스 디코우더의 구성을 나타낸 블럭도.3 is a block diagram showing the configuration of the address decoder of the present invention.

Claims (3)

ROM과 RAM과 RTC 및 다수의 REG의 슬라이브 디바이스가 구비된 로컬 메모리(1)와, 어드레스와 데이타 신호선들을 분리시키는 어드레스 래치(2) 및 데이타 래치(2a)(2b)(2c)(2d)들과, 트랜잭션의 호출 영역을 구분하는 스페이서 디코우더(4)와, 로컬 메모리 내의 각 디바이스들을 선택하는 로컬 디바이스(5)와, 내부의 각 라인들을 선택적으로 연결하는 라인 선택부(6)들로 구성됨을 특징으로 하는 로커 버스 콘트롤 서브 유니트.Local memory (1) equipped with ROM, RAM, RTC, and multiple REG slave devices, address latches (2) and data latches (2a) (2b) (2c) (2d) that separate address and data signal lines And a spacer decoder 4 for distinguishing a call area of a transaction, a local device 5 for selecting respective devices in a local memory, and line selectors 6 for selectively connecting respective lines therein. Rocker bus control subunit, characterized in that consisting of. 제1항에 있어서, 어드레스 래치와 데이타 래치를 양방향성으로 구성한 로컬 버스 콘트롤 서브 유니트.The local bus control subunit of claim 1, wherein the address latch and the data latch are configured bidirectionally. 제1항에 있어서, 스페이서 디코우더에서 출력되는 로컬 메모리 신호가 입력 되어야만 로컬 디코우더에서 각 디바이스를 선택하는 신호를 출력 하도록 구성한 로컬 버스 콘트롤 서브 유니트.The local bus control subunit of claim 1, wherein the local decoder outputs a signal for selecting each device in the local decoder only when a local memory signal output from the spacer decoder is input. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890019505A 1989-12-26 1989-12-26 Local bus control subunit KR920002667B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890019505A KR920002667B1 (en) 1989-12-26 1989-12-26 Local bus control subunit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890019505A KR920002667B1 (en) 1989-12-26 1989-12-26 Local bus control subunit

Publications (2)

Publication Number Publication Date
KR910012939A true KR910012939A (en) 1991-08-08
KR920002667B1 KR920002667B1 (en) 1992-03-31

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ID=19293644

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890019505A KR920002667B1 (en) 1989-12-26 1989-12-26 Local bus control subunit

Country Status (1)

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KR (1) KR920002667B1 (en)

Also Published As

Publication number Publication date
KR920002667B1 (en) 1992-03-31

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