KR980007341A - Alarm communication device between processor and device of electronic switchboard - Google Patents

Alarm communication device between processor and device of electronic switchboard Download PDF

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Publication number
KR980007341A
KR980007341A KR1019960020143A KR19960020143A KR980007341A KR 980007341 A KR980007341 A KR 980007341A KR 1019960020143 A KR1019960020143 A KR 1019960020143A KR 19960020143 A KR19960020143 A KR 19960020143A KR 980007341 A KR980007341 A KR 980007341A
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KR
South Korea
Prior art keywords
processor
alarm signal
devices
signal
registers
Prior art date
Application number
KR1019960020143A
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Korean (ko)
Other versions
KR100197424B1 (en
Inventor
이재설
Original Assignee
유기범
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019960020143A priority Critical patent/KR100197424B1/en
Publication of KR980007341A publication Critical patent/KR980007341A/en
Application granted granted Critical
Publication of KR100197424B1 publication Critical patent/KR100197424B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54566—Intelligent peripherals, adjunct processors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M2201/00—Electronic components, circuits, software, systems or apparatus used in telephone systems
    • H04M2201/34—Microprocessors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13106—Microprocessor, CPU
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13393—Time slot switching, T-stage, time slot interchanging, TSI

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

본 발명은 타임 슬롯 스위치(2)를 이용하여 프로세서(1)와 디바이스(2-1∼2-4)들이 타임 슬롯화된 데이터로 통신하는 전전자 교환기에 관한 것으로서, 디바이스(2-1∼2-4)들은 상태 알람 신호 및 케이블 착탈 알람 신호를 각각 출력하게 구성되며; 타임 슬롯 스위치(2)는 상기 디바이스(2-1∼2-4)들의 상기 열람 신호 및 케이블 착탈 알람 신호를 각각 저장하는 레지스터(R1, R2)들을 구비하며; 프로세서(1)는 어드레스 라인(A)을 통하여 레지스터(R1, R2)를 지정하는 어드레서 신호를 출력하고, 어드레스 신호에 의하여 지정된 레지스터(R1, R2) 들로부터 출력되는 알람 신호를 데이터 라인(D)을 통하여 입력하도록 구성된다.The present invention relates to an electronic switch in which the processor 1 and the devices 2-1 to 2-4 communicate with time slotted data using the time slot switch 2, wherein the devices 2-1 to 2 are provided. -4) are configured to output a status alarm signal and a cable detachment alarm signal respectively; The time slot switch (2) has registers (R1, R2) for storing the browsing signal and the cable detachment alarm signal of the devices (2-1 to 2-4), respectively; The processor 1 outputs an addresser signal specifying the registers R1 and R2 through the address line A, and outputs an alarm signal output from the registers R1 and R2 designated by the address signal to the data line D. It is configured to input through).

즉, 본 발명은 타임 슬롯 스위치를 이용하여 프로세서와 디바이스간의 데이터를 통신할 수 있게 한 전전자교환기에서 디바이스들의 알람 신호를 프로세서의 제어에 따라 프로세서에 입력할 수 있다는 효과가 있다.That is, the present invention has an effect that the alarm signal of the devices can be input to the processor under the control of the processor in the electronic switch that enables the data exchange between the processor and the device using the time slot switch.

Description

전전자 교환기의 프로세서와 디바이스간 알람 통신 장치Alarm communication device between processor and device of electronic switchboard

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 전전자 교환기의 프로세서와 디바이스간 알람 통신 장치의 블록도.1 is a block diagram of an alarm communication device between a processor and a device of an electronic switching system according to the present invention.

제2도는 본 발명에 따른 전전자 교환기의 프로세서와 디바이스간 알람 통신 장치내 타임 슬롯 스위치에 구성되는 레지스터의 상태도.2 is a state diagram of a register configured in a time slot switch in an alarm communication device between a processor and a device of an electronic switching system according to the present invention.

Claims (1)

타임 슬롯 스위치(2)를 이용하여 프로세서(1)와 디바이스(2-1∼2-4)들이 타임 슬롯화된 데이터로 1통신하는 전전자 교환기에 있어서, 상기 디바이스(2-1∼2-4)들은 상태 알람 신호 및 케이블 착탈 알람 신호를 각각 출력하게 구성되며; 상기 타임 슬롯 스위치(2)는 상기 디바이스(2-1∼2-4)들의 상기 열람 신호 및 케이블 착탈 알람 신호를 각각 저장하는 레지스터(R1, R2)들을 구비하며; 상기 프로세서(1)는 어드레서 라인(A)을 통하여 레지스터(R1, R2)를 지정하는 어드레서 신호를 출력하고, 상기 어드레스 신호에 의하여 지정된 상기 레지스터(R1, R2) 들로부터 출력되는 알람 신호를 데이터 라인(D)을 통하여 입력하도록 구성된 전전자 교환기의 프로세서와 디바이스간 알람 통신 장치.In an all-electronic exchange in which the processor 1 and the devices 2-1 to 2-4 communicate with each other by time slotted data using the time slot switch 2, the devices 2-1 to 2-4. ) Are configured to output a status alarm signal and a cable detachment alarm signal, respectively; The time slot switch (2) has registers (R1, R2) for storing the read signal and cable detachment alarm signal of the devices (2-1 to 2-4), respectively; The processor 1 outputs an address signal specifying registers R1 and R2 through an address line A, and outputs an alarm signal output from the registers R1 and R2 specified by the address signal. An alarm communication device between a processor and a device of an electronic switchgear configured to be input through a data line (D).
KR1019960020143A 1996-06-05 1996-06-05 Apparatus for communicating alarm signal processor with device in switching system KR100197424B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960020143A KR100197424B1 (en) 1996-06-05 1996-06-05 Apparatus for communicating alarm signal processor with device in switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960020143A KR100197424B1 (en) 1996-06-05 1996-06-05 Apparatus for communicating alarm signal processor with device in switching system

Publications (2)

Publication Number Publication Date
KR980007341A true KR980007341A (en) 1998-03-30
KR100197424B1 KR100197424B1 (en) 1999-06-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960020143A KR100197424B1 (en) 1996-06-05 1996-06-05 Apparatus for communicating alarm signal processor with device in switching system

Country Status (1)

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Also Published As

Publication number Publication date
KR100197424B1 (en) 1999-06-15

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