KR920010616A - Chip Enable Detection Circuit - Google Patents

Chip Enable Detection Circuit Download PDF

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Publication number
KR920010616A
KR920010616A KR1019900018295A KR900018295A KR920010616A KR 920010616 A KR920010616 A KR 920010616A KR 1019900018295 A KR1019900018295 A KR 1019900018295A KR 900018295 A KR900018295 A KR 900018295A KR 920010616 A KR920010616 A KR 920010616A
Authority
KR
South Korea
Prior art keywords
chip enable
detection circuit
enable detection
inverter
receiving
Prior art date
Application number
KR1019900018295A
Other languages
Korean (ko)
Other versions
KR930011351B1 (en
Inventor
안희태
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900018295A priority Critical patent/KR930011351B1/en
Publication of KR920010616A publication Critical patent/KR920010616A/en
Application granted granted Critical
Publication of KR930011351B1 publication Critical patent/KR930011351B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

내용 없음.No content.

Description

칩 인에이블 검출회로Chip Enable Detection Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 칩인에이블 검출회로도,4 is a chip enable detection circuit diagram according to the present invention;

제5도는 본 발명에 회로에 따른 동작타이밍도.5 is an operation timing diagram according to the circuit of the present invention.

Claims (2)

칩 인에이블 검출회로를 구성함에 있어서, 어드레스 검출신호에 의해 동작되는 데이타 래치 및 리셋회로(20)를 이용하여 칩 셀렉트 입력신호(, CS2)를 래치하고, 칩 인에이블 검출회로의 발생을 어드레스 검출신호가 억제할수 있도록 구성한 것을 특징으로 하는 칩 인에이블 검출회로.In configuring the chip enable detection circuit, the chip select input signal (using the data latch and reset circuit 20 operated by the address detection signal) is used. And latching CS2) so that the address detection signal can suppress the generation of the chip enable detection circuit. 제1항에 있어서, 데이타 래치 및 리셋회로(20)는 어드레스 검출신호를 게이트로 인가받아 동작하는 피모오스 및 엔모오스 트랜지스터(20P,20N)와, 상기 피모오스 및 앤모오스 트랜지스터(20P,20N)의 출력과 인버터(11)와 낸드게이트(14)를 통한 칩셀렉터 입력신호(,CS2)를 입력으로 받는 노아게이트(16)와, 상기 노아게이트(16)의 출력을 입력받아 상기 피모오스 트랜지스터 (20P)의 소오스단으로 인가하는 인버터(13)를 포함하여 구성되는 것을 특징으로 하는 칩인에이블 검출회로.2. The data latch and reset circuit 20 of claim 1, wherein the data latch and reset circuit 20 is operated by receiving an address detection signal as a gate. And the chip selector input signal through the inverter 11 and the NAND gate 14 And an inverter 13 receiving the CS2 as an input and an inverter 13 receiving the output of the NOA gate 16 and applying it to a source terminal of the PMOS transistor 20P. Chip enable detection circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900018295A 1990-11-13 1990-11-13 Chip enable detecting circuit KR930011351B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900018295A KR930011351B1 (en) 1990-11-13 1990-11-13 Chip enable detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900018295A KR930011351B1 (en) 1990-11-13 1990-11-13 Chip enable detecting circuit

Publications (2)

Publication Number Publication Date
KR920010616A true KR920010616A (en) 1992-06-26
KR930011351B1 KR930011351B1 (en) 1993-11-30

Family

ID=19305924

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900018295A KR930011351B1 (en) 1990-11-13 1990-11-13 Chip enable detecting circuit

Country Status (1)

Country Link
KR (1) KR930011351B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100432914B1 (en) * 2002-03-05 2004-05-22 썬스타 산업봉제기계 주식회사 Photo-film for detecting syncro-signal, Motor controller decorated that, Methode for setting up a position of a neddle support using that
KR100482995B1 (en) * 2002-09-06 2005-04-15 주식회사 하이닉스반도체 Nonvolatile ferroelectric memory device
KR100487919B1 (en) * 2002-08-30 2005-05-09 주식회사 하이닉스반도체 Device for controlling non-volatile ferroelectric memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100719363B1 (en) * 2005-05-20 2007-05-17 삼성전자주식회사 Memory device ? Indicator circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100432914B1 (en) * 2002-03-05 2004-05-22 썬스타 산업봉제기계 주식회사 Photo-film for detecting syncro-signal, Motor controller decorated that, Methode for setting up a position of a neddle support using that
KR100487919B1 (en) * 2002-08-30 2005-05-09 주식회사 하이닉스반도체 Device for controlling non-volatile ferroelectric memory
KR100482995B1 (en) * 2002-09-06 2005-04-15 주식회사 하이닉스반도체 Nonvolatile ferroelectric memory device

Also Published As

Publication number Publication date
KR930011351B1 (en) 1993-11-30

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