KR960039627A - Input buffer of synchronous memory device - Google Patents

Input buffer of synchronous memory device Download PDF

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Publication number
KR960039627A
KR960039627A KR1019950008098A KR19950008098A KR960039627A KR 960039627 A KR960039627 A KR 960039627A KR 1019950008098 A KR1019950008098 A KR 1019950008098A KR 19950008098 A KR19950008098 A KR 19950008098A KR 960039627 A KR960039627 A KR 960039627A
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KR
South Korea
Prior art keywords
source
drain
gate input
signal
memory device
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Application number
KR1019950008098A
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Korean (ko)
Inventor
이상호
신광섭
박근영
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950008098A priority Critical patent/KR960039627A/en
Publication of KR960039627A publication Critical patent/KR960039627A/en

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  • Static Random-Access Memory (AREA)

Abstract

본 발명은 지연부를 사용하지 않고도 입력측 클럭에 의한 신호(K-PULSE)의 폭에 관계없이 K-PULSE가 로우에서 하이가될 때만 유효한 데이타를 갖고 있으면 그 데이타가 어드레스 버퍼 내부의 래치회로에 저장되도록 함으로써 셋업 타임과 홀드 타입의 특성을 개선하는 동기식 메모리소자의 입력버퍼에 관한 것이다.In the present invention, regardless of the width of the signal (K-PULSE) by the input side clock without using a delay unit, if the data has valid data only when K-PULSE goes from low to high, the data is stored in the latch circuit inside the address buffer. The present invention relates to an input buffer of a synchronous memory device which improves the setup time and hold type characteristics.

Description

동기식 메모리소자의 입력버퍼Input buffer of synchronous memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 어드레스 버퍼의 회로 구성도, 제4도는 제3도의 신호 파형도.3 is a circuit configuration diagram of an address buffer according to the present invention, and FIG. 4 is a signal waveform diagram of FIG.

Claims (1)

외부신호(AIN)를 게이트 입력으로 하고 소스는 VCC에 연결된 PMOS1; 외부신호(AIN)를 게이트 입력으로 하고 소스는 VCC에 연결된 NMOS1; 상기 PMOS1의 드레인이 소스에 연결되고, 클럭에 의한 신호(K-PULSE. N)를 게이트 입력으로 받는 PMOS2; 상기 NMOS1의 드레인이 소스에 연결되고 반전수단을 거친 클럭에 의한 신호를 게이트 입력으로 받는 NMOS2; 상기 PMOS2의 드레인과 NMOS2의 드레인에 연결되는 제1래치부; 클럭에 의한 신호(K-PULSE, N)를 게이트 입력으로, 소스는 상기 제1래치부의 출력과 PMOS3의 소스에 연결된 NMOS3; 반전수단을 거친 클럭에 의한 신호를 게이트 입력으로, 소스는 상기 제1래치부의 출력과 NMOS3의 소스에 연결된 PMOS3; 상기 PMOS3의 드레인과 NMOS3의 드레인에 연결된 제2래치부를 포함하여 구성되는 것을 특징으로 하는 동기식 메모리소자의 입력버퍼.A PMOS1 having an external signal AIN as a gate input and a source connected to V CC ; NMOS1 having an external signal AIN as a gate input and a source connected to V CC ; A PMOS2 connected to a drain of the PMOS1 and receiving a clock signal (K-PULSE.N) as a gate input; A NMOS2 connected to a source of the drain of the NMOS1 and receiving a signal from a clock that has passed through an inverting means as a gate input; A first latch part connected to the drain of the PMOS2 and the drain of the NMOS2; A signal of a clock (K-PULSE, N) as a gate input, the source of which is connected to an output of the first latch portion and a source of PMOS3; A signal inputted by a clock through the inverting means as a gate input, the source comprising: a PMOS3 coupled to an output of the first latch portion and a source of NMOS3; And a second latch portion connected to the drain of the PMOS3 and the drain of the NMOS3. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019950008098A 1995-04-07 1995-04-07 Input buffer of synchronous memory device KR960039627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008098A KR960039627A (en) 1995-04-07 1995-04-07 Input buffer of synchronous memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008098A KR960039627A (en) 1995-04-07 1995-04-07 Input buffer of synchronous memory device

Publications (1)

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KR960039627A true KR960039627A (en) 1996-11-25

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KR1019950008098A KR960039627A (en) 1995-04-07 1995-04-07 Input buffer of synchronous memory device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474991B1 (en) * 1997-07-29 2005-05-27 삼성전자주식회사 Input buffer and input buffering method of semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474991B1 (en) * 1997-07-29 2005-05-27 삼성전자주식회사 Input buffer and input buffering method of semiconductor memory device

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