KR930014579A - Address buffer circuit - Google Patents

Address buffer circuit Download PDF

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Publication number
KR930014579A
KR930014579A KR1019910024919A KR910024919A KR930014579A KR 930014579 A KR930014579 A KR 930014579A KR 1019910024919 A KR1019910024919 A KR 1019910024919A KR 910024919 A KR910024919 A KR 910024919A KR 930014579 A KR930014579 A KR 930014579A
Authority
KR
South Korea
Prior art keywords
output
channel transistor
address buffer
gate
buffer circuit
Prior art date
Application number
KR1019910024919A
Other languages
Korean (ko)
Other versions
KR940008141B1 (en
Inventor
이종석
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910024919A priority Critical patent/KR940008141B1/en
Publication of KR930014579A publication Critical patent/KR930014579A/en
Application granted granted Critical
Publication of KR940008141B1 publication Critical patent/KR940008141B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

본 발명은 어드레스 버퍼회로에 관한 것이며, 특히, 종래의 어드레스 버퍼회로에, 추가의 N채널 트랜지스터 및 캐패시터를 구성시켜 잡음을 감쇠시킬뿐 아니라, 속도를 빠르게한 어드레스 버퍼회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address buffer circuit, and more particularly, to an address buffer circuit in which conventional N-channel transistors and capacitors are formed in the conventional address buffer circuit to not only attenuate noise but also to speed up.

Description

어드레스 버퍼 회로Address buffer circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 어드레스 버퍼 회로도.3 is an address buffer circuit diagram according to the present invention.

제4도는 본 발명에 따른 어드레스 버퍼 회로의 신호 파형도.4 is a signal waveform diagram of an address buffer circuit according to the present invention;

Claims (2)

어드레스 입력(ADD)과, 상기 어드레스 입력(ADD) 신호를 게이트 단자에서 수신하는 P채널 트랜지스터(P3) 및 N채널 트랜지스터(N3)와, 상기 P채널 트랜지스터(P3)와 직렬로 연결된 P채널 트랜지스터(P4)와, 상기 N채널 트랜지스터(N3)와 병렬로 연결된 N채널 트랜지스터(N4)로 구성된 노어 게이트(NOR)와, 상기 노어 게이트(NOR)의 출력이 인버터(INV4,INV5)를 거쳐 출력되는 출력(A) 및 상기 노어 게이트(NOR)의 출력이 인버터(INV4,INV5,INV6)를 거쳐 출력되는 출력(A)을 구비하는 어드레스 버퍼회로에 있어서, 어드레스 입력(ADD)과 인버터(INV4)의 출력사이에 구성되는 캐패시터(C1)와, 노어 게이트(NOR)의 출력이 드레인 단자가 되고 상기 인버터(INV4)의 출력이 게이트 단자가 되는 N채널 트랜지스터(N5)를 포함하는 것을 특징으로 하는 어드레스 버퍼회로.A P-channel transistor P3 and an N-channel transistor N3 for receiving an address input ADD, the address input ADD signal at a gate terminal, and a P-channel transistor connected in series with the P-channel transistor P3; P4), a NOR gate NOR composed of an N-channel transistor N4 connected in parallel with the N-channel transistor N3, and an output from which the output of the NOR gate NOR is output through the inverters INV4 and INV5. An address buffer circuit having an output (A) in which (A) and the output of the NOR gate (NOR) are output through inverters INV4, INV5, and INV6, wherein an address input ADD and an output of inverter INV4 are provided. An address buffer comprising a capacitor C 1 formed therebetween and an N-channel transistor N5 in which an output of the NOR gate NOR becomes a drain terminal and an output of the inverter INV4 becomes a gate terminal. Circuit. 제1항에 있어서, 캐피시터 C1는 어드레스 입력(ADD) 데이타를, 인버터(INV4)를 거친 정션(C)으로 전달하는 전하쉐어링(charge sharing)역활을 하는 것을 특징으로 하는 어드레스 버퍼회로.2. The address buffer circuit according to claim 1, wherein the capacitor C 1 plays a charge sharing role of transferring the address input data to the junction C via the inverter INV4. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910024919A 1991-12-28 1991-12-28 Adress buffer circuit KR940008141B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910024919A KR940008141B1 (en) 1991-12-28 1991-12-28 Adress buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910024919A KR940008141B1 (en) 1991-12-28 1991-12-28 Adress buffer circuit

Publications (2)

Publication Number Publication Date
KR930014579A true KR930014579A (en) 1993-07-23
KR940008141B1 KR940008141B1 (en) 1994-09-03

Family

ID=19326479

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910024919A KR940008141B1 (en) 1991-12-28 1991-12-28 Adress buffer circuit

Country Status (1)

Country Link
KR (1) KR940008141B1 (en)

Also Published As

Publication number Publication date
KR940008141B1 (en) 1994-09-03

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