KR920009078A - Dual Voltage Source Interface Circuit - Google Patents

Dual Voltage Source Interface Circuit Download PDF

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Publication number
KR920009078A
KR920009078A KR1019900016388A KR900016388A KR920009078A KR 920009078 A KR920009078 A KR 920009078A KR 1019900016388 A KR1019900016388 A KR 1019900016388A KR 900016388 A KR900016388 A KR 900016388A KR 920009078 A KR920009078 A KR 920009078A
Authority
KR
South Korea
Prior art keywords
voltage source
interface circuit
source interface
dual voltage
inverter
Prior art date
Application number
KR1019900016388A
Other languages
Korean (ko)
Inventor
한교진
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019900016388A priority Critical patent/KR920009078A/en
Priority to JP2401074A priority patent/JPH04150411A/en
Priority to DE4040046A priority patent/DE4040046C1/de
Priority to IT02239290A priority patent/IT1244339B/en
Priority to GB9027194A priority patent/GB2248988A/en
Priority to NL9100046A priority patent/NL9100046A/en
Priority to FR9100305A priority patent/FR2668001A1/en
Priority to CN91100202A priority patent/CN1060724A/en
Publication of KR920009078A publication Critical patent/KR920009078A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음No content

Description

이중전압원 인터페이스회로Dual Voltage Source Interface Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명 이중전압원 인터페이스회로의 개략적인 블록 구성도.2 is a schematic block diagram of a dual voltage source interface circuit of the present invention.

제3도는 본 발명 이중전압원 인터페이스 회로의 상세회로도.3 is a detailed circuit diagram of the dual voltage source interface circuit of the present invention.

제4도는 본 발명 이중전압원 인터페이스회로의 각부 입출력 파형도이다.4 is an input / output waveform diagram of each part of the dual voltage source interface circuit of the present invention.

Claims (2)

게이트로 입력신호(Vin)가 인가되는 n채널의 CMOS트랜지스터(n1)와, 입력신호(Vin)를 반전시키는 인버터(IVa) 및 이 인버터(IVa)의 출력을 게이트로 입력하는 n채널의 CMOS트랜지스터(n2)를 구비하여 상기 CMOS트랜지스터(n1, n2)의 드레인 사이에 고전압원(VH)을 갖는 래치회로(1)를 연결하여서 된 이중전압원 인터페이스 회로.N-channel CMOS transistor n 1 to which the input signal Vin is applied to the gate, inverter IV a to invert the input signal Vin, and n-channel to input the output of the inverter IVa to the gate. CMOS transistor (n 2) in the CMOS transistor (n 1, n 2) of a double hayeoseo connected to the latch circuit (1) having a high voltage source (V H) between the drain voltage source interface circuit comprising a. 제1항에 있어서, 래치회로(1)가 인버터(Ivb, Ivc)로 구성된 이중전압원 인터페이스회로.2. The dual voltage source interface circuit as claimed in claim 1, wherein the latch circuit (1) comprises an inverter (I vb , I vc ). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900016388A 1990-10-15 1990-10-15 Dual Voltage Source Interface Circuit KR920009078A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
KR1019900016388A KR920009078A (en) 1990-10-15 1990-10-15 Dual Voltage Source Interface Circuit
JP2401074A JPH04150411A (en) 1990-10-15 1990-12-10 Double voltage source interface circuit
DE4040046A DE4040046C1 (en) 1990-10-15 1990-12-14
IT02239290A IT1244339B (en) 1990-10-15 1990-12-14 DOUBLE VOLTAGE INTERFACE CIRCUIT
GB9027194A GB2248988A (en) 1990-10-15 1990-12-14 Interface circuits
NL9100046A NL9100046A (en) 1990-10-15 1991-01-11 INTERFACE SWITCHING WITH DOUBLE SOURCE VOLTAGE.
FR9100305A FR2668001A1 (en) 1990-10-15 1991-01-11 INTERFACE CIRCUIT FOR DOUBLE VOLTAGE SOURCE.
CN91100202A CN1060724A (en) 1990-10-15 1991-01-12 The interface circuit of double voltage source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900016388A KR920009078A (en) 1990-10-15 1990-10-15 Dual Voltage Source Interface Circuit

Publications (1)

Publication Number Publication Date
KR920009078A true KR920009078A (en) 1992-05-28

Family

ID=19304696

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900016388A KR920009078A (en) 1990-10-15 1990-10-15 Dual Voltage Source Interface Circuit

Country Status (8)

Country Link
JP (1) JPH04150411A (en)
KR (1) KR920009078A (en)
CN (1) CN1060724A (en)
DE (1) DE4040046C1 (en)
FR (1) FR2668001A1 (en)
GB (1) GB2248988A (en)
IT (1) IT1244339B (en)
NL (1) NL9100046A (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432467A (en) * 1993-05-07 1995-07-11 Altera Corporation Programmable logic device with low power voltage level translator
US5508653A (en) * 1993-09-29 1996-04-16 Acc Microelectronics Corporation Multi-voltage circuit arrangement and method for accommodating hybrid electronic system requirements
JP3204848B2 (en) * 1994-08-09 2001-09-04 株式会社東芝 Level conversion circuit and method for outputting level-converted data using the level conversion circuit
KR100223744B1 (en) * 1995-12-29 1999-10-15 김영환 Mixed voltage input buffer
JP3258229B2 (en) * 1996-03-18 2002-02-18 株式会社東芝 Level conversion circuit and semiconductor integrated circuit
DE19844674A1 (en) * 1998-09-29 1999-12-16 Siemens Ag Logic level converter for level shifter
US7005893B1 (en) 1999-07-19 2006-02-28 University Of Southern California High-performance clock-powered logic
WO2001006656A1 (en) * 1999-07-19 2001-01-25 University Of Southern California High-performance clock-powered logic
JP3701942B2 (en) 2003-01-21 2005-10-05 沖電気工業株式会社 Level conversion circuit
JP4667190B2 (en) * 2005-09-29 2011-04-06 パナソニック株式会社 Level conversion circuit
JP4702261B2 (en) * 2005-11-24 2011-06-15 富士電機システムズ株式会社 Level shift circuit
JP2017168965A (en) * 2016-03-15 2017-09-21 力晶科技股▲ふん▼有限公司 Level shift circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5087746A (en) * 1973-12-07 1975-07-15
US4039862A (en) * 1976-01-19 1977-08-02 Rca Corporation Level shift circuit
JPS5775027A (en) * 1980-10-29 1982-05-11 Nec Corp Level shift circuit
CA1175503A (en) * 1981-07-17 1984-10-02 Andreas Demetriou Cmos turn-on circuit
US4644185A (en) * 1985-05-03 1987-02-17 National Semiconductor Corporation Self clocking CMOS latch
JPS6269719A (en) * 1985-09-24 1987-03-31 Toshiba Corp Level conversion logic circuit
US4695744A (en) * 1985-12-16 1987-09-22 Rca Corporation Level shift circuit including source follower output
US4897567A (en) * 1988-10-13 1990-01-30 Harris Corporation Fast level translator circuit
US4978870A (en) * 1989-07-19 1990-12-18 Industrial Technology Research Institute CMOS digital level shifter circuit

Also Published As

Publication number Publication date
CN1060724A (en) 1992-04-29
IT9022392A1 (en) 1992-06-14
IT9022392A0 (en) 1990-12-14
JPH04150411A (en) 1992-05-22
GB2248988A (en) 1992-04-22
DE4040046C1 (en) 1992-04-02
NL9100046A (en) 1992-05-06
IT1244339B (en) 1994-07-08
GB9027194D0 (en) 1991-02-06
FR2668001A1 (en) 1992-04-17

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A201 Request for examination
SUBM Surrender of laid-open application requested