JP2017168965A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To configure a level shift circuit that converts a signal that has voltage relations of V1<V2 and V1≤V3<V4 and that changes between V1 and V2 into a signal that changes between V3 and V4.SOLUTION: A level shift circuit comprises: a first inverter that inverts an input voltage; a latch circuit configured by cascade-connecting second to fifth inverters, and that keeps a state of the input voltage and outputs an output voltage of the fifth inverter as an output voltage of the level shift circuit; a first transistor circuit in which a first PMOS transistor and a first NMOS transistor applied with V3 and a second NMOS transistor applied with the input voltage are connected in series, and that pulls down an output voltage of the second inverter when V2 is inputted; and a second transistor circuit in which a second PMOS transistor and a third NMOS transistor applied with V3 and a fourth NMOS transistor applied with the input voltage are connected in series, and that pulls down an output voltage of the third inverter when V1 is inputted.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a level shift circuit used in, for example, a semiconductor memory device.

  Conventionally, the breakdown voltage problem of antifuse circuits is well known. Since the fuse element of the antifuse circuit is destroyed at a high voltage, the antifuse circuit itself needs to withstand the high voltage. The control signal for controlling the antifuse circuit has a voltage change range (swing) from a low voltage of 1.2 V to the ground voltage, for example. Thereafter, the low voltage is shifted to the high voltage side of the antifuse circuit.

  FIG. 1 is a circuit diagram showing a configuration of an antifuse circuit according to a conventional example. In FIG. 1, the antifuse circuit includes two P-channel MOS transistors Q1 and Q2 and a fuse cell FC1. The control voltage Vg2 is a voltage for controlling the data value stored in the fuse cell FC1, and the control voltage Vg1 is a voltage for destroying the fuse cell FC1.

US Pat. No. 9,197,200

  Here, in order to generate the control voltage Vg1, a level shift circuit for converting a signal changing from 0V to 1.2V into a signal changing from 0V to 8.1V is required. At this time, the breakdown voltage of the gate voltage of the MOS transistor Q1 becomes a problem.

For example, Patent Document 1 discloses a specific example of the above-described level shift circuit, and the level shift circuit according to the conventional example includes:
(1) an input voltage processing circuit comprising two inverters for sequentially inverting the input voltage to be input;
(2) An output voltage processing circuit including two inverters constituting a latch circuit that latches a voltage signal from each inverter via a capacitor.

The level shift circuit according to this conventional example has the following problems because the input voltage processing circuit and the output voltage processing circuit are connected using a capacitor.
(1) Immediately after the power is turned on, the voltage latched by the latch circuit becomes uncertain.
(2) When the voltage difference between the power supply voltage of the input voltage processing circuit and the power supply voltage of the output voltage processing circuit is large, the level shift circuit does not operate.

  In order to solve the above problems, an object of the present invention is to provide a level shift circuit that converts a signal that changes between a first voltage and a second voltage into a signal that changes between a third voltage and a fourth voltage. The object of the present invention is to provide a structure that is simpler than that of the prior art and that can operate reliably.

The level shift circuit according to the present invention has a voltage relationship of first voltage <second voltage and first voltage ≦ third voltage <fourth voltage, and the first voltage to the second voltage. A level shift circuit that shifts a level of an input voltage that changes at a third output voltage to an output voltage that changes at a fourth voltage,
A first inverter for inverting the input voltage;
A latch circuit configured by cascading second to fifth inverters, maintaining a state of the input voltage and outputting an output voltage of the fifth inverter as an output voltage of the level shift circuit;
A first P-channel MOS transistor and a first N-channel MOS transistor to which the third voltage is applied as a control voltage, respectively, and a second N-channel MOS transistor to which the input voltage is applied as a control voltage are connected in series. A first transistor circuit configured to pull down the output voltage of the second inverter when the input voltage of the second voltage is input; and
A second P-channel MOS transistor and a third N-channel MOS transistor to which the third voltage is applied as a control voltage, respectively, and a fourth N-channel MOS transistor to which the input voltage is applied as a control voltage are connected in series. And a second transistor circuit that pulls down the output voltage of the third inverter when the input voltage of the first voltage is input.

  In the level shift circuit, the high-voltage side power supply voltage of the first inverter is set to the second voltage, the low-voltage side power supply voltage of the first inverter is set to the first voltage, and the first voltage The high-voltage power supply voltage of the second to fifth inverters is set to the fourth voltage, and the low-voltage power supply voltage of the second to fifth inverters is set to the third voltage. To do.

  Further, in the level shift circuit, the second and third inverters are configured to have a first driving capability, and the fourth and fifth inverters have a second driving capability stronger than the first driving capability. It is characterized by having a driving capability.

  Therefore, according to the level shift circuit of the present invention, the signal that changes between the first voltage and the second voltage is changed from the third voltage to the fourth voltage (the first voltage <the second voltage and the first voltage). The level shift circuit for converting to a signal that changes in the following condition: voltage ≦ third voltage <fourth voltage) can be configured to be surely operated with a simple configuration compared to the prior art. Here, if it can be converted into a signal that changes between the third voltage and the fourth voltage, the withstand voltage of the MOS transistor to which the voltage signal is applied can be lowered.

It is a circuit diagram which shows the structure of the antifuse circuit which concerns on a prior art example. It is a circuit diagram which shows the structure of the general level shift circuit which concerns on a comparative example. It is a circuit diagram which shows the structure of the level shift circuit which concerns on embodiment.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  If the present inventor can realize a level shift circuit that converts a signal that changes from 0 V to a low voltage into a voltage signal that changes from an intermediate voltage to a high voltage (low voltage <intermediate voltage <high voltage), the voltage signal is applied. In view of reducing the withstand voltage of the MOS transistor, a level shift circuit according to an embodiment described later has been invented.

  FIG. 2 is a circuit diagram showing a configuration of a general level shift circuit according to a comparative example. 2, the level shift circuit according to the comparative example includes two P-channel MOS transistors (hereinafter referred to as PMOS transistors) Q11 and Q12, two N-channel MOS transistors (hereinafter referred to as NMOS transistors) Q13 and Q14, and an inverter. And INV1.

  First, when Vs1 = Vs2 = 0V, if the input voltage range is 0V to 1.2V and the output voltage range is 0V to 8.1V, for example, the withstand voltages of the MOS transistors Q11 and Q12 are If it is 6V, the level shift circuit does not operate. In order to solve this withstand voltage problem, when the output voltage range is changed from 2.7 V to 8.1 V, even if Vs1 = Vs2 = 2.7 V, the MOS transistors Q13 and Q14 are not turned on. The level shift circuit does not operate. In order to solve the above problems, the present inventors have invented the level shift circuit of FIG.

  FIG. 3 is a circuit diagram showing a configuration of the level shift circuit according to the embodiment. In FIG. 3, 0V, 1.2V, 2.7V, and 8.1V are voltage examples, respectively, and the minimum voltage, the low voltage, and the intermediate voltage that have the voltage relationship of the lowest voltage <low voltage It may be a voltage or a high voltage. The minimum voltage may be a ground voltage, a negative voltage, or a positive voltage lower than a low voltage.

In FIG. 3, the level shift circuit according to the embodiment is
(1) A configuration in which two inverters INV11 and INV12 each having a first driving capability and two inverters INV13 and INV14 each having a second driving capability stronger than the first driving capability are connected in cascade. Latch circuit 101,
(2) A transistor circuit 103 configured by connecting a PMOS transistor Q21 and NMOS transistors Q22 and Q23 in series, and a transistor circuit 104 configured by connecting a PMOS transistor and Q31 and NMOS transistors Q32 and Q33 in series. A turn-on and off circuit 102 comprising:
(3) An inverter INV10 that inverts the input voltage Vin is provided.
Here, the level shift circuit of FIG. 3 is characterized in that a voltage signal in a voltage change range of 0V to 1.2V is voltage-shifted to a voltage signal in a voltage change range of 2.7V to 8.1V.

  In the latch circuit 101, the high-voltage power supply voltage of each inverter INV11 to INV14 is set to 8.1V, and the low-voltage power supply voltage is set to 2.7V. The inverters INV11 and INV12 have a first driving capability that is weaker than the second driving capability of the inverters INV13 and 14, while the inverters INV13 and INV14 have a second driving capability that is stronger than the first driving capability of the inverters INV11 and 12. Have Here, the driving ability of each of the inverters INV11 to INV14 can be realized by changing the size of the MOS transistors constituting the inverters as is well known. This driving capability setting can reduce the current consumption of the circuit operation with respect to the change of the input voltage Vin, while increasing the driving capability for the load of the output voltage Vout of the level shift circuit, but this driving capability setting is optional. However, this is not an essential configuration of the present invention.

  The input voltage Vin is applied to the gate of the MOS transistor Q23 and is also applied to the gate of the MOS transistor Q33 via the inverter INV10. The high-voltage power supply voltage of the inverter INV10 is set to 1.2V, and the low-voltage power supply voltage is set to 0V.

  The transistor circuit 103 is configured by connecting a PMOS transistor Q21 and NMOS transistors Q22 and Q23 in series. A gate bias voltage of 2.7 V is applied to the gates of the MOS transistors Q21 and Q22, and the gate of the MOS transistor Q23 is applied. The input voltage Vin is applied. In the transistor circuit 103, the PMOS transistors Q21 and Q22 operate as voltage limiters, and the MOS transistor Q23 operates as a pull-down driver.

  The transistor circuit 104 is configured by connecting a PMOS transistor Q31 and NMOS transistors Q32 and Q33 in series. A gate bias voltage of 2.7 V is applied to the gates of the MOS transistors Q31 and Q32. The output voltage from the inverter INV10 is applied to the gate. Note that the drains of the MOS transistors Q23 and Q33 are set to a ground voltage of 0V. In the transistor circuit 104, the PMOS transistors Q31 and Q32 operate as a voltage limiter, and the MOS transistor Q33 operates as a pull-down driver.

  The operation of the level shift circuit configured as described above will be described separately when the input voltage Vin is 0V, which is a low level, and when it is 1.2V, which is a high level. Note that the output voltage of the inverter V11 is V11, and the output voltage of the inverter V12 is V12. The drain voltage of the MOS transistor Q21 is V21d, and the drain voltage of the MOS transistor Q22 is V22d. Further, the drain voltage of the MOS transistor Q31 is set to V31d, and the drain voltage of the MOS transistor Q32 is set to V32d.

(A) When the output voltage V12 is 8.1V and the input voltage Vin is 0V which is a low level:
The drain voltage V31d of the MOS transistor Q31 is 8.1V and the drain / source current I31ds flows. However, when the drain voltage V31d becomes 2.7V + Vth (Vth is the threshold voltage of the MOS transistor Q31), the drain / source current I31ds. Stops flowing. At this time, the drain voltage V32d of the MOS transistor Q32 is limited to 2.7 V-Vth (Vth is the threshold voltage of the MOS transistor Q32), and the drain-source voltage of the MOS transistor Q33 is protected by the MOS transistor Q32. At this time, the MOS transistor Q33 is turned on by the gate voltage of 1.2V, and the source / drain current I33sd flows through the MOS transistor Q33. That is, the transistor circuit 104 becomes a pull-down circuit, and the output voltage V12 of the inverter V12 is pulled down to 4V. At this time, the output voltage of the inverter INV13 of the latch circuit 101 becomes high level, the output voltage of the inverter INV14 becomes low level, and the output voltage Vout = 2.7V is output.

(B) When the output voltage V11 is 8.1V and the input voltage Vin is high level 1.2V:
The drain voltage V21d of the MOS transistor Q21 is 8.1V and the drain / source current I21ds flows. When the drain voltage V21d becomes 2.7V + Vth (Vth is the threshold voltage of the MOS transistor Q21), the drain / source current I21ds Stops flowing. At this time, the drain voltage V22d of the MOS transistor Q22 is limited to 2.7 V-Vth (Vth is the threshold voltage of the MOS transistor Q22), and the drain-source voltage of the MOS transistor Q23 is protected by the MOS transistor Q22. At this time, the MOS transistor Q23 is turned on by the gate voltage of 1.2V, and the source / drain current I23sd flows through the MOS transistor Q23. That is, the transistor circuit 103 becomes a pull-down circuit, and the output voltage V11 of the inverter V11 is pulled down to 4V. At this time, the output voltage of the inverter INV12 of the latch circuit 101 becomes high level, the output voltage of the inverter INV13 becomes low level, the output voltage of the inverter INV14 becomes high level, and the output voltage Vout = 8.1V is output.

  The level shift circuit configured as described above outputs the output voltage Vout = 2.7V (intermediate voltage) when the input voltage Vin = 0V, while the output voltage Vout = 8.V when the input voltage Vin = 1.2V. 1V (high voltage) is output. That is, the level shift circuit level-shifts a voltage signal in the voltage change range of 0V to 1.2V to a voltage signal in the voltage change range of 2.7V to 8.1V and outputs the voltage signal.

  Therefore, according to the level shift circuit of the present embodiment, the level shift circuit that converts a signal that changes from 0 V to a low voltage into a signal that changes from an intermediate voltage to a high voltage (low voltage <intermediate voltage <high voltage), Compared to the prior art, the configuration is simple and can be configured to operate reliably.

  The voltage in FIG. 3 is an example, and 0V, 1.2V, 2.7V, and 8.1V are respectively the lowest voltage having a voltage relationship of lowest voltage <low voltage <intermediate voltage <high voltage, It may be a low voltage, an intermediate voltage, or a high voltage. The minimum voltage may be a ground voltage, a negative voltage, or a positive voltage lower than a low voltage. That is, in the present embodiment, a level shift circuit that has a voltage relationship of V1 <V2 <V3 <V4 and converts a signal that changes in V1 to V2 into a signal that changes in V3 to V4 is configured. Here, the level shift circuit connects the first inverter for inverting the input voltage and the second to fifth inverters in cascade to maintain the state of the input voltage, and level shifts the output voltage of the fifth inverter. A latch circuit that outputs as an output voltage of the circuit, a first PMOS transistor and a first NMOS transistor to which V3 is applied, and a second NMOS transistor to which an input voltage is applied are connected in series and V2 is input. A first transistor circuit that pulls down the output voltage of the second inverter, a second PMOS transistor and a third NMOS transistor to which V3 is applied, and a fourth NMOS transistor to which the input voltage is applied, Are connected in series and when V1 is input, the second transistor circuit pulls down the output voltage of the third inverter Equipped with a.

  In the above embodiment, a level shift circuit that has a voltage relationship of V1 <V2 <V3 <V4 and converts a signal that changes in V1 to V2 into a signal that changes in V3 to V4 is configured. The present invention is not limited to this, and the operation is possible even in a voltage relationship of V1 <V2 and V1 ≦ V3 <V4, and may be set as such.

  The level shift circuit disclosed in the above embodiments can be applied to various nonvolatile semiconductor memory devices such as flash memory, DRAM, and SRAM, or volatile semiconductor memory devices.

  Note that the gate voltage applied to each gate of the MOS transistors Q21 to Q33 is a control voltage for turning on or off the MOS transistors Q21 to Q33.

101 ... Latch circuit,
102 ... turn-on and off circuit,
103, 104 ... transistor circuit,
FC1 ... fuse cell,
INV1 to INV14 ... inverter,
Q1-Q33: MOS transistors.

Claims (3)

An input voltage having a voltage relationship of first voltage <second voltage and first voltage ≦ third voltage <fourth voltage, and changing from the first voltage to the second voltage, A level shift circuit that shifts a level to an output voltage that changes in a range from a voltage to a fourth voltage,
A first inverter for inverting the input voltage;
A latch circuit configured by cascading second to fifth inverters, maintaining a state of the input voltage and outputting an output voltage of the fifth inverter as an output voltage of the level shift circuit;
A first P-channel MOS transistor and a first N-channel MOS transistor to which the third voltage is applied as a control voltage, respectively, and a second N-channel MOS transistor to which the input voltage is applied as a control voltage are connected in series. A first transistor circuit configured to pull down the output voltage of the second inverter when the input voltage of the second voltage is input; and
A second P-channel MOS transistor and a third N-channel MOS transistor to which the third voltage is applied as a control voltage, respectively, and a fourth N-channel MOS transistor to which the input voltage is applied as a control voltage are connected in series. And a second transistor circuit that pulls down the output voltage of the third inverter when the input voltage of the first voltage is input. 7. A level shift circuit, comprising: The high-voltage power supply voltage of the first inverter is set to the second voltage, the low-voltage power supply voltage of the first inverter is set to the first voltage,
The high voltage side power supply voltage of the second to fifth inverters is set to the fourth voltage, and the low voltage side power supply voltage of the second to fifth inverters is set to the third voltage. 2. The level shift circuit according to claim 1, wherein:   The second and third inverters are configured to have a first driving capability, and the fourth and fifth inverters are configured to have a second driving capability stronger than the first driving capability. The level shift circuit according to claim 1 or 2, wherein

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