CN1060724A - The interface circuit of double voltage source - Google Patents

The interface circuit of double voltage source Download PDF

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Publication number
CN1060724A
CN1060724A CN91100202A CN91100202A CN1060724A CN 1060724 A CN1060724 A CN 1060724A CN 91100202 A CN91100202 A CN 91100202A CN 91100202 A CN91100202 A CN 91100202A CN 1060724 A CN1060724 A CN 1060724A
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CN
China
Prior art keywords
voltage source
phase inverter
interface circuit
input signal
mentioned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN91100202A
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Chinese (zh)
Inventor
韩教真
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN1060724A publication Critical patent/CN1060724A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

The present invention is the interface circuit of double voltage source, comprising: grid is connected to the n channel CMOS transistors n of input signal Vin 1, make an anti-phase IV of above-mentioned input signal Vin aAnd grid is connected to above-mentioned phase inverter IV aA n channel CMOS transistors n of output 2, above-mentioned CMOS transistor n 1And n 2Drain electrode between by being connected to high-voltage power supply V HLatch circuit 1 connect.

Description

The interface circuit of double voltage source
The present invention relates to semiconductor circuit, specifically, relate to the interface circuit that class is used low-voltage and two kinds of supply voltages of high voltage, can be driven the double voltage source of high voltage circuit with low-voltage source.
In general, the interface circuit of the double voltage source of two kinds of supply voltages of existing use as shown in Figure 1, by phase inverter IV 1And IV 2Constitute phase inverter IV 1And IV 2Again by n channel CMOS transistors n 1, n 2And P channel CMOS transistors P 1, P 2Form.Wherein, the phase inverter IV of P channel CMOS transistors P and n channel CMOS transistors n formation 1, be connected to low-voltage source (about 3.3V), P channel CMOS transistors P 2And n channel CMOS transistors n 2The output phase inverter IV that constitutes 2
In addition, input signal Vin has the fluctuation of 0～3.3V.Like this, when input signal changes to high level by low level or changes to low level by high level, phase inverter IV 1Just have the output Vmid of 0～3.3V; Phase inverter IV 1Output Vmid when in low-voltage, fluctuating, be connected to high voltage source V HThe output phase inverter IV of (about 5V) will make high voltage fluctuate.At this moment, if phase inverter IV 1Output Vmid be OV, then by output phase inverter IV 2P channel CMOS transistors P 2With resistance R 1To form current path, output Vout will become high voltage 5V; If phase inverter IV is output as 3.3V, output phase inverter IV 2P channel CMOS transistors P 2To end n channel CMOS transistors n 2With conducting, output Vout promptly becomes low-voltage (about OV).
Even phase inverter IV like this, 1Output Vmid when being 3.3V, output phase inverter IV 2In P channel CMOS transistors P 2The grid source electrode between voltage Vgs be 5V-3.3V=1.7V, also be in certain conducting state; Like this, direct current fails to be convened for lack of a quorum by CMOS transistor P 2And impedance R 1Flow, thus the shortcoming that causes electrical source consumption to increase.In addition, suppose resistance R in this case 1No, output Vout will be owing to CMOS transistor P 2Conducting and become high voltage mistakenly.
Purpose of the present invention promptly is to eliminate the above-mentioned shortcoming that existing double voltage source interface circuit has, and aims to provide a kind ofly can avoid the power wastage that causes because of flowing of unnecessary DC current, the double voltage source interface circuit of realizing the butt joint between two kinds of supply voltages.
To achieve these goals, double voltage source interface circuit of the present invention comprises that grid is connected to the n channel CMOS transistors n of input signal Vin 1, make a phase inverter IV of above-mentioned input signal Vin paraphase aAnd grid is connected to above-mentioned phase inverter IV aA n channel CMOS transistors of output n 2, above-mentioned n channel CMOS transistors n 1And n 2Drain electrode between by being connected to high power supply V HLatch circuit 1 connect.
Describe effect of the present invention with reference to the accompanying drawings in detail.In the accompanying drawing,
Fig. 1. be the structural drawing of existing dual power supply interface circuit.
Fig. 2. be the simple block diagram of double voltage source interface circuit of the present invention.
Fig. 3. be the detailed circuit diagram of double voltage source interface circuit of the present invention.
Fig. 4. be the input and output oscillogram of the each several part of double voltage source interface circuit of the present invention.
In the accompanying drawing, 1 is latch circuit, n 1, n 2Be n channel CMOS transistors, P 1, P 2Be P channel CMOS transistors, IV 1, IV 2, IV 3～IV CPhase inverter.From n channel CMOS transistors n 1Grid input low-voltage (OV-3.3V) input signal as Fig. 4 (A) and 4(B), to latch circuit 1 supply high voltage (about 5V) supply voltage V H, by phase inverter IV aTo n channel CMOS transistors n 2Grid the inversion signal Vin of input signal Vin is provided.Like this, CMOS transistor n 1During conducting, CMOS transistor n 2To end, on the contrary, as CMOS transistor n 1When ending, CMO transistor n 2To lead.
In addition, the signal on the node on the node among two node P and the Q will be output in the latch circuit 1.When input signal Vin by when changing between the OV to 3.3, Fig. 4 (A) and 4(B) shown in latch circuit output Vout will from low level fade to high level (when input signal Vin when OV fades to 3.3V), or from high level transformation low level (when input signal Vin when 3.3V fades to OV).
Like this, the node P in latch circuit 1 is that noble potential (5V), some Q are under the occasion of electronegative potential (OV), when input signal Vin moves to high level with low level (Fig. 4 (A)), is in the CMOS transistor n of cut-off state 1To enter conducting state, phase inverter IV aTo make CMOS transistor n 2Enter into cut-off state by conducting state, therefore, by CMOS transistor n 1To form current path, the current potential of node P will move to OV.Like this, the characteristic of latch circuit is improved, and the output Vout of latch circuit 1 is the noble potential that the current potential of node Q will move to 5V, and current path all interdicts, thereby can keep stable output Vout.
In addition, be electronegative potential (OV) at the node P of latch circuit 1, when node Q is noble potential (5V), input signal Vin (Fig. 4 (B)) when noble potential moves to low level is in the CMOS transistor n of conducting state 1To enter cut-off state phase inverter IV aTo make CMOS transistor n 2Enter conducting state from cut-off state, therefore, by CMOS transistor n 2To form current path, the output Vout of the current potential of node Q that is latch circuit 1 will become the low level of OV and maintain on this level.
If adopt of the present invention double voltage supply interface circuit with above-mentioned effect, just can avoid because of input signal low level (loss of DC current on one in the output of latch circuit two nodes that 0～3.3V) fluctuation causes, thus can reach the advantage that reduces unnecessary power loss.

Claims (2)

1, double voltage source interface circuit is characterized in that:
This circuit comprises:
Grid is connected to the n channel CMOS transistors n of input signal Vin 1
Make an anti-phase phase inverter IV of above-mentioned input signal Vin a,
The output of above-mentioned phase inverter IV is imported one channel CMOS transistors n of its grid 2
Above-mentioned CMOS transistor n 1, and n 2Drain electrode between by being connected to high voltage source V HLatch circuit 1 connects.
2, double voltage source interface circuit as claimed in claim 1, it is characterized in that: above-mentioned latch circuit is by phase inverter IV bAnd IV cConstitute).
CN91100202A 1990-10-15 1991-01-12 The interface circuit of double voltage source Pending CN1060724A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019900016388A KR920009078A (en) 1990-10-15 1990-10-15 Dual Voltage Source Interface Circuit
KR16388 1990-10-15

Publications (1)

Publication Number Publication Date
CN1060724A true CN1060724A (en) 1992-04-29

Family

ID=19304696

Family Applications (1)

Application Number Title Priority Date Filing Date
CN91100202A Pending CN1060724A (en) 1990-10-15 1991-01-12 The interface circuit of double voltage source

Country Status (8)

Country Link
JP (1) JPH04150411A (en)
KR (1) KR920009078A (en)
CN (1) CN1060724A (en)
DE (1) DE4040046C1 (en)
FR (1) FR2668001A1 (en)
GB (1) GB2248988A (en)
IT (1) IT1244339B (en)
NL (1) NL9100046A (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432467A (en) * 1993-05-07 1995-07-11 Altera Corporation Programmable logic device with low power voltage level translator
US5508653A (en) * 1993-09-29 1996-04-16 Acc Microelectronics Corporation Multi-voltage circuit arrangement and method for accommodating hybrid electronic system requirements
JP3204848B2 (en) * 1994-08-09 2001-09-04 株式会社東芝 Level conversion circuit and method for outputting level-converted data using the level conversion circuit
KR100223744B1 (en) * 1995-12-29 1999-10-15 김영환 Mixed voltage input buffer
JP3258229B2 (en) * 1996-03-18 2002-02-18 株式会社東芝 Level conversion circuit and semiconductor integrated circuit
DE19844674A1 (en) * 1998-09-29 1999-12-16 Siemens Ag Logic level converter for level shifter
WO2001006656A1 (en) * 1999-07-19 2001-01-25 University Of Southern California High-performance clock-powered logic
US7005893B1 (en) 1999-07-19 2006-02-28 University Of Southern California High-performance clock-powered logic
JP3701942B2 (en) 2003-01-21 2005-10-05 沖電気工業株式会社 Level conversion circuit
JP4667190B2 (en) * 2005-09-29 2011-04-06 パナソニック株式会社 Level conversion circuit
JP4702261B2 (en) * 2005-11-24 2011-06-15 富士電機システムズ株式会社 Level shift circuit
JP2017168965A (en) * 2016-03-15 2017-09-21 力晶科技股▲ふん▼有限公司 Level shift circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5087746A (en) * 1973-12-07 1975-07-15
US4039862A (en) * 1976-01-19 1977-08-02 Rca Corporation Level shift circuit
JPS5775027A (en) * 1980-10-29 1982-05-11 Nec Corp Level shift circuit
CA1175503A (en) * 1981-07-17 1984-10-02 Andreas Demetriou Cmos turn-on circuit
US4644185A (en) * 1985-05-03 1987-02-17 National Semiconductor Corporation Self clocking CMOS latch
JPS6269719A (en) * 1985-09-24 1987-03-31 Toshiba Corp Level conversion logic circuit
US4695744A (en) * 1985-12-16 1987-09-22 Rca Corporation Level shift circuit including source follower output
US4897567A (en) * 1988-10-13 1990-01-30 Harris Corporation Fast level translator circuit
US4978870A (en) * 1989-07-19 1990-12-18 Industrial Technology Research Institute CMOS digital level shifter circuit

Also Published As

Publication number Publication date
IT9022392A0 (en) 1990-12-14
IT1244339B (en) 1994-07-08
FR2668001A1 (en) 1992-04-17
NL9100046A (en) 1992-05-06
GB2248988A (en) 1992-04-22
IT9022392A1 (en) 1992-06-14
DE4040046C1 (en) 1992-04-02
GB9027194D0 (en) 1991-02-06
KR920009078A (en) 1992-05-28
JPH04150411A (en) 1992-05-22

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