JPH0338919A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To prevent the operation of a field effect transistor(TR) pair in an unsaturated region and to obtain a differential amplifier circuit with a fast speed, higher circuit integration and low power consumption by providing a level shift circuit respectively between drains of 1st and 2nd field effect TR and 1st and 2nd output terminals. CONSTITUTION:First and 2nd field effect TRs 11, 12, 1st and 2nd output terminals (b), (c) and 1st and 2nd level shift means VL1, VL2 inserted between drains of the 1st and 2nd field effect TRs 11, 12 and the 1st and 2nd output terminals (b), (c) are provided. Moreover, 1st and 2nd load means 14, 15 inserted between the 1st and 2nd output terminals (b), (c) and a power supply voltage Vcc respectively are provided in the title differential amplifier circuit. Thus, the level shift circuits VL1, VL2 keeping a high speed operation and evading the TRs 11, 12 from being operated in the unsaturation region are simplified to obtain the differential amplifier circuit with high circuit integration and low power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention J (Field of Industrial Application) This invention relates to a differential amplifier circuit provided with a level shift circuit.

(Prior Art) A differential amplifier circuit using field effect transistors can realize high-speed operation with low power consumption, and is also suitable for miniaturization of elements. Among them, the Schottky gate field effect transistor, the so-called MESFET (IIet
Al semiconductor FET) has a simple structure and manufacturing process, and is therefore suitable for miniaturizing the gel length.

FIG. 4 is a circuit diagram showing the configuration of a conventional differential amplifier circuit using MES FETs. A constant current Fj13 is inserted between the common node a of each source of MESFET II and 12 and the ground voltage Vss.

Also, a load resistor 14 whose one end is connected to the power supply voltage VCC
The other end is connected to the drain of transistor 11. Also, a load resistor 1 whose one end is connected to the power supply voltage Vcc
The other end of 5 is connected to the drain of transistor 12. The connection node between the drain of the transistor 1.1 and the resistor 14 is one output terminal 16 from which one signal Q is output.
The connection node C with 5 is the other output terminal 17, from which the other signal Q is output.

A transistor 18 and a constant voltage source 19 are inserted in series between the gate of the transistor 11 and the power supply voltage Vcc, and a constant current source 20 is inserted between the gate of the transistor 11 and the ground voltage VSS to form a level shift circuit. 21 is configured, and a human input signal V is applied to the gate of the transistor 18.
an is supplied. Furthermore, 1117 transistors 22 and constant voltage sources 23 are connected in series between the gate of the transistor 12 and the power supply voltage VCC.
A constant 7B current source 24 is inserted between the gate of the transistor 22 and the ground voltage Vss to form a level shift circuit 25, and the gate of the transistor 22 is supplied with an input signal Vln inverse to the input signal Vln. .

In order to operate the differential amplifier circuit as described above stably and at high speed, it is necessary to operate the transistors 1.1.12 in the saturation region shown in the waveform diagram of FIG.

In the case of a field effect transistor, a sufficient voltage between the drain and source is required to operate in the saturation region, and term 4 of the stable point A is calculated from the gate-source voltage VCS of the transistor as shown in the figure. The transistor's r!
The value obtained by subtracting the threshold value Vtu which is 1 (Vcs - V
r□).

By the way, in order to reduce the size of the transistor and speed up its operation, if the threshold value of the differential transistor is a negative value, the conductance gm will be larger, and the relationship between the operating current and the capacitance of the transistor will be moderate. It is preferable. Therefore, the threshold voltage of each transistor 11, 12 of the differential amplifier circuit is negative. Therefore, the stable point A (V
GS VTH) is naturally large, and therefore it is necessary to provide the level shift circuits 21 and 25 at the signal input section, respectively.

That is, when the human input signal Vln is applied to the gate of the transistor 18 at "H level", a signal lowered by a certain level shift Mjt by the transistor 18 and the constant voltage source 19 is applied to the gate of the transistor 11. It maintains a gate-source voltage and becomes conductive.At this time, the current SS flows through the load resistor 14 due to the constant current source 13, and the potential of the node b of the drain of the transistor 11 is equal to the resistance of the load resistor 14. value R
If it is set to 1, the potential will be lower than Vce by the voltage of I ssX R1. In order for this transistor 1l to operate in the saturation region shown in the waveform diagram of FIG.
If the source-drain voltage of 1 is Vosl, the gate-source voltage is Vcst, and the L threshold is VTHI, then V is 51 VTIII < VDSI
- Must be (1).

Equation (1) above indicates that the drain voltage must be greater than the gate voltage for the field effect transistor to operate, and therefore, the level shift circuit 2
1 is provided to prevent the gate potential of the transistor 11 from becoming higher than Vcc-IssXR1. The level shift circuit 22 is also provided for the same purpose.

The level shift amounts of the level shift circuits 21 and 22 are determined by the threshold values of the respective transistors 11 and 12. In order to make this threshold negative and achieve high-speed operation, this source follower type level shift circuit 2 is used to prevent the transistor from operating in the non-saturation region.
L22 will be needed. However, when considering the installation of a circuit with a higher degree of integration, the source follower type level shift circuit increases its area and consumes a considerable amount of power, which poses a problem.

(Problem to be Solved by the Invention) As described above, conventionally, in order to realize high-speed operation of the differential pair field effect transistors, the threshold value thereof is set to be negative. Accordingly, a source follower type level shift circuit is required to prevent the transistor from operating in a non-saturation region. However, when considering the design of circuits with higher integration,
This level shift circuit is problematic because it occupies an increased area and consumes considerable power.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to maintain the same high-speed operation as before,
In order to avoid transistors operating in the non-saturation region, the level shift circuit is simplified and has a higher degree of integration.
Moreover, the object is to provide a differential amplifier circuit with low power consumption.

[Structure of the Invention] (Means for Solving the Problems) A differential amplifier circuit of the present invention has two components whose sources are connected in common.
1 and 2 field effect transistors, 1st and 2nd output terminals, and between the drains of the 1st and 2nd field effect transistors and the 1st and 2nd output terminals, respectively. and first and second load means inserted between the first and second output terminals and the power supply voltage, respectively.

(Function) In the present invention, in order to simplify the level shift circuit for preventing the first and second field effect transistors from operating in a non-saturation region, the drains of the first and second field effect transistors and the A level shift circuit is provided between each of the first and second output terminals to prevent the field effect transistor pair from operating in a non-saturation region.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 shows the configuration of the differential j-bone width circuit of the present invention, in which MES FET (metal semiconductor
2 is a diagram illustrating a configuration of an embodiment of a differential amplifier circuit using a differential amplifier circuit (FET). MESFETII,
A constant current [13 is interposed between the common node a of each of the 12 sources and the ground voltage VSS.

Also, a load resistor 14 whose one end is connected to the power supply voltage Vcc
The other end is connected to the drain of transistor 11 via level shift circuit VLI. Also, one end is connected to the electric Fj
, the other end of the load resistor 15 connected to the voltage Vcc is connected to the drain of the transistor 12 via a level shift circuit VL2. The gate of the transistor 11 is supplied with an input signal Vin, and the gate of the transistor 12 is supplied with a human input signal Vln having a phase opposite to that of the human input signal Vln. The level shift circuit VLI and the resistor 1
A connection node b between the level shift circuit VL2 and the resistor 15 is an output terminal 16, and a signal Q is output therefrom, and a connection node C between the level shift circuit VL2 and the resistor 15 is an output terminal 17, and a signal Q is output therefrom.

The operation of the above embodiment circuit will be explained. When the human power Vln is at "H" level, the transistor 11 becomes conductive. Since the current Iss flows through the resistor 14 and VLI due to the constant current i13, the potential at the node b becomes higher than the voltage at the drain of the transistor 11 by a certain level set by VLI, and the voltage between the gate and source of the transistor 11 increases. can be maintained at a voltage greater than the voltage of Similarly, node C also has VL2 lower than the drain voltage of transistor 12.
The potential increases by a certain level set in , and can be maintained higher than the gate-source voltage of the transistor 12.

FIG. 2 shows a level shift circuit V of the embodiment circuit shown in FIG. 1 above.
FIG. 2 is a circuit diagram showing a specific configuration of LI and VL2. That is, this shows a configuration in which resistors 31.32 are used for VLI and VL2, and the level shift amount is set by the resistance value of resistors 31.32.

FIG. 3 shows the level shift circuit V of the embodiment circuit shown in FIG. 1 above.
FIG. 3 is a circuit diagram showing another specific configuration of L1 and VL2.

That is, MES FET33.3 is used for VLI and VL2.
4, and the drain and gate of each are short-circuited.

In this case, the level shift amount is MES FET33.3
A fine level shift amount can be set by adjusting the threshold value and gate width of each of the four types. As a result, the differential transistor 11
．． The voltage at the output node of transistor No. 12 can be made larger than the voltage between the gate and source of transistor No. 12 with a small amount of level shift, and operation in the saturation region can be achieved. Voltage margin can be easily secured.

According to the circuit configuration shown in FIGS. 2 and 3, the number of elements is reduced compared to the conventional level shift circuit, and the degree of integration is further improved. In addition, the level shift circuit 22
．． Since the source follower stage like 23 (shown in FIG. 4) is eliminated, power consumption is reduced, and since the human input signal is directly input to the differential transistor pair of the switch stage, faster operation is possible.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a differential amplifier circuit that operates at high speed, has a higher degree of fflvi, and has low tl′l power consumption.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a configuration according to an embodiment of the present invention, and FIG.
3 and 3 are circuit diagrams showing the specific configuration of the embodiment circuit shown in FIG. 1, FIG. 4 is a circuit diagram showing the configuration of a conventional differential amplifier circuit, and FIG. 5 is a saturation of a field effect transistor. FIG. 3 is a waveform diagram for explaining region operation. II, 12...MES FET, 13...constant current source, 14, 15...resistor, VLI, VL2...level shift circuit. Figure 2 Figure VGS-VT)-1 DS Figure

Claims (3)

[Claims] (1) first and second field effect transistors whose sources are commonly connected; first and second output terminals; drains of the first and second field effect transistors and the first and second field effect transistors; first and second level shift means respectively inserted between the output terminals of the first and second output terminals, and first and second load means respectively inserted between the first and second output terminals and the power supply voltage. A differential amplifier circuit characterized by comprising: (2) The differential amplifier circuit according to claim 1, wherein the first and second level shift means each include a resistor element. (3) The differential amplifier circuit according to claim 1, wherein said first and second level shift means are each comprised of a field effect transistor.