JPS5775027A - Level shift circuit - Google Patents

Level shift circuit

Info

Publication number
JPS5775027A
JPS5775027A JP55151795A JP15179580A JPS5775027A JP S5775027 A JPS5775027 A JP S5775027A JP 55151795 A JP55151795 A JP 55151795A JP 15179580 A JP15179580 A JP 15179580A JP S5775027 A JPS5775027 A JP S5775027A
Authority
JP
Japan
Prior art keywords
level shift
level
voltages
vss3
inverters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55151795A
Other languages
Japanese (ja)
Inventor
Yasushi Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55151795A priority Critical patent/JPS5775027A/en
Publication of JPS5775027A publication Critical patent/JPS5775027A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the power consumption due to through-currents by shifting the level gradually by cascaded level shift parts. CONSTITUTION:A clock phi and a clock inversion phi inverted by inverters 2 and 3 are inputted to level shift parts 100(2) and 100(3). A constant voltage VDD and voltages VSS1, VSS2 and VSS3 which becomes larger toward the succecding stage are applied to inverters 2 and 3 and level shift parts 100(2) and 100(3) as operating voltages. A digital signal displaced between voltages VDD and VSS3 is obtained from an outut terminal OUT. At this time, since the level is shifted in plural stages divisionally, through-currents of level shift patts 100(2) and 100(3) are reduced.
JP55151795A 1980-10-29 1980-10-29 Level shift circuit Pending JPS5775027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55151795A JPS5775027A (en) 1980-10-29 1980-10-29 Level shift circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55151795A JPS5775027A (en) 1980-10-29 1980-10-29 Level shift circuit

Publications (1)

Publication Number Publication Date
JPS5775027A true JPS5775027A (en) 1982-05-11

Family

ID=15526458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55151795A Pending JPS5775027A (en) 1980-10-29 1980-10-29 Level shift circuit

Country Status (1)

Country Link
JP (1) JPS5775027A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04150411A (en) * 1990-10-15 1992-05-22 Samsung Electron Co Ltd Double voltage source interface circuit
US5942915A (en) * 1996-09-09 1999-08-24 Nec Corporation Level shift circuit formed by two cascaded CMOS inverters

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04150411A (en) * 1990-10-15 1992-05-22 Samsung Electron Co Ltd Double voltage source interface circuit
US5942915A (en) * 1996-09-09 1999-08-24 Nec Corporation Level shift circuit formed by two cascaded CMOS inverters

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