KR970012702A

KR970012702A - Asynchronous Semiconductor Memory Device Using Synchronous Semiconductor Memory Device

Info

Publication number: KR970012702A
Application number: KR1019950027236A
Authority: KR
Inventors: 장경호
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-08-29
Filing date: 1995-08-29
Publication date: 1997-03-29

Abstract

본 발명은 동기형 반도체 메모리 장치를 이용한 비동기형 반도체 메모리 장치를 공개한다. 그 장치는 클럭신호에 응답하여 동작을 수행하는 동기형 반도체 모밀 장치, 및 상기 동기형 반도체 메모리 장치로 입력되는 어드레스의 상태 천이를 검출하여 상기 클럭신호를 발생하기 위한 어드레스 상태 천이 검출퍼스 발생회로로 구성되어 있다. 따라서, 비동기형 반도체 메모리 장치를 별도로 설계할 필요없이 동기형 반도체 메모리 장치를 이용하여 비동기형 반도체 메모리 장치를 구성할 수 있다.The present invention discloses an asynchronous semiconductor memory device using a synchronous semiconductor memory device. The apparatus includes a synchronous semiconductor integrator that performs an operation in response to a clock signal, and an address state transition detection circuit for detecting the state transition of an address input to the synchronous semiconductor memory device and generating the clock signal. Consists of. Therefore, the asynchronous semiconductor memory device can be configured using the synchronous semiconductor memory device without designing the asynchronous semiconductor memory device separately.

Description

Asynchronous Semiconductor Memory Device Using Synchronous Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 동기형 반도체 메모리 장치를 이용한 비동기형 반도체 메모리 장치의 구성 블럭도이다.1 is a block diagram illustrating the construction of an asynchronous semiconductor memory device using the synchronous semiconductor memory device of the present invention.

제2도는 본 발명의 비동기형 반도체 메모리 장치의 어드레스 상태천이 검출펄스 발생회로를 나타내는 것이다.2 shows an address state transition detection pulse generating circuit of the asynchronous semiconductor memory device of the present invention.

Claims

A synchronous semiconductor memory device performing an operation in response to a clock signal; And an address state transition detection pulse generation circuit for detecting a state transition of an address input to the synchronous semiconductor memory device and generating the clock signal. .

2. The apparatus of claim 1, wherein the address state transition detection pulse generation circuit comprises: first and second delay means for delaying a plurality of address signals, respectively; A first NAND gate for inputting the plurality of address signals, respectively, and non-multiplying the output signals of the first delay means; A first NOR gate for inputting the plurality of address signals and inputting the output signals of the first delay means, respectively, for non- logical sum; A second NAND gate for inputting the output signals of the first NAND gate and non-multiplying the plurality of address signals, respectively; A second NOR gate for inputting the plurality of address signals and non-logically inputting the output signals of the first NOR gate, respectively; Inverters for inverting output signals of the second NAND gate, respectively; A first buffer for buffering the wired-OR signals of the output signals of the inverters and the output signals of the second NOR gate; And a second buffer for generating the clock signal by buffering the outer-eared signals of the output signals of the first buffers.

3. The asynchronous semiconductor memory device using a synchronous semiconductor memory device according to claim 2, wherein the delay time of said first delay means is longer than the delay time of said second delay means.

※ Note: The disclosure is based on the initial application.