KR970051268A - Internal Clock Generation Circuit of Semiconductor Memory Device - Google Patents

Internal Clock Generation Circuit of Semiconductor Memory Device Download PDF

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Publication number
KR970051268A
KR970051268A KR1019950065881A KR19950065881A KR970051268A KR 970051268 A KR970051268 A KR 970051268A KR 1019950065881 A KR1019950065881 A KR 1019950065881A KR 19950065881 A KR19950065881 A KR 19950065881A KR 970051268 A KR970051268 A KR 970051268A
Authority
KR
South Korea
Prior art keywords
generation circuit
internal clock
memory device
semiconductor memory
clock generation
Prior art date
Application number
KR1019950065881A
Other languages
Korean (ko)
Inventor
강경우
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950065881A priority Critical patent/KR970051268A/en
Publication of KR970051268A publication Critical patent/KR970051268A/en

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Abstract

본 발명은 반도체 메모리 장치를 내부클릭 발생회로에 관한 것으로서, 특히 복수의 입력 신호들을 하나의 노드로 입력하고 이 노드신호에 응답하여 용량이 큰 부하를 구동하기 위한 제1내부클럭신호를 발생하는 복수의 제1회로들; 및 복수의 제1회로들의 상기 노드신호들을 병합하여 마스터 클럭신호로 사용하기 위하여 제2클럭신호를 발생하는 제2회로를 구비한 것을 특징으로 한다. 따라서 본 발명에서는 클럭신호들 사이의 스큐를 줄일 수 있고 스피드를 개선할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal click generation circuit, and more particularly, to input a plurality of input signals to one node and generate a first internal clock signal for driving a large load in response to the node signal. First circuits of; And a second circuit for generating a second clock signal for merging the node signals of the plurality of first circuits and using the node signals as a master clock signal. Therefore, in the present invention, skew between clock signals can be reduced and speed can be improved.

Description

반도체 메모리 장치의 내부클럭 발생 회로Internal Clock Generation Circuit of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 반도체 메모리 장치의 내부클럭 발생회로의 구성을 나타낸 회로도,3 is a circuit diagram showing a configuration of an internal clock generation circuit of a semiconductor memory device according to the present invention;

제4도는 본 발명에 의한 내부클럭 발생회로의 일예를 나타낸 회로도.4 is a circuit diagram showing an example of an internal clock generation circuit according to the present invention.

Claims (1)

어드레스를 버퍼하기 위한 어드레스 버퍼; 상기 어드레스 버퍼의 출력신호를 입력하여 소정수의 구동신호를 발생하기 위한 소정수의 구동수단; 및 소정수의 구동수단으로 부터의 구동신호를 입력하여 동작하는 소정수의 회로군을 구비한 것을 특징으로 하는 반도체 메모리 장치An address buffer for buffering the address; A predetermined number of driving means for inputting an output signal of the address buffer to generate a predetermined number of driving signals; And a predetermined number of circuit groups operating by inputting driving signals from the predetermined number of driving means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065881A 1995-12-29 1995-12-29 Internal Clock Generation Circuit of Semiconductor Memory Device KR970051268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065881A KR970051268A (en) 1995-12-29 1995-12-29 Internal Clock Generation Circuit of Semiconductor Memory Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065881A KR970051268A (en) 1995-12-29 1995-12-29 Internal Clock Generation Circuit of Semiconductor Memory Device

Publications (1)

Publication Number Publication Date
KR970051268A true KR970051268A (en) 1997-07-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065881A KR970051268A (en) 1995-12-29 1995-12-29 Internal Clock Generation Circuit of Semiconductor Memory Device

Country Status (1)

Country Link
KR (1) KR970051268A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464399B1 (en) * 1998-05-12 2005-04-06 삼성전자주식회사 Internal Clock Signal Generator and Method for Synchronous Storage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100464399B1 (en) * 1998-05-12 2005-04-06 삼성전자주식회사 Internal Clock Signal Generator and Method for Synchronous Storage

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