KR970055510A - Improved bungee transition detector - Google Patents
Improved bungee transition detector Download PDFInfo
- Publication number
- KR970055510A KR970055510A KR1019950065855A KR19950065855A KR970055510A KR 970055510 A KR970055510 A KR 970055510A KR 1019950065855 A KR1019950065855 A KR 1019950065855A KR 19950065855 A KR19950065855 A KR 19950065855A KR 970055510 A KR970055510 A KR 970055510A
- Authority
- KR
- South Korea
- Prior art keywords
- inverter
- output signal
- signal
- inverting
- transition detector
- Prior art date
Links
Landscapes
- Static Random-Access Memory (AREA)
Abstract
본 발명은 비동기 메모리에 관한 것으로, 특히, 전체 레이아웃의 면적을 줄인 수 있으며, 속도를 향상 시킬 수 있는 번지 이행 검출기(Address Transition Detector : 이하 ATD라 한다.)에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to asynchronous memory, and more particularly, to an address transition detector (ATD), which can reduce an area of an entire layout and improve speed.
본 발명은 입력 단자에 인가된 입력 신호를 반전 출력하는 제1인버터; 상기 제1인버터의 반전 신호를 얻기 위한 제2인버터; 펄스 폭을 조절하기 위하여 상기 제1인버터의 출력 신호를 반전과 비반전을 거듭하는 버퍼부; 및 상기 버퍼 블록의 출력 신호와 상기 버퍼 블록의 최종 비반전 되는 출력 신호에 응답하여 상기 제1인버터의 출력 신호 또는 상기 제2인버터의 신호를 출력단자에 전달하는 익스 클루시브 오어 게이트부를 구비한 것을 특징으로 한다.The present invention includes a first inverter for inverting and outputting an input signal applied to an input terminal; A second inverter for obtaining an inverted signal of the first inverter; A buffer unit for inverting and non-inverting the output signal of the first inverter to adjust a pulse width; And an exclusive or gate part configured to transmit an output signal of the first inverter or a signal of the second inverter to an output terminal in response to an output signal of the buffer block and a final non-inverted output signal of the buffer block. It features.
따라서, 본 발명은 회로가 간단하므로 반복구조를 갖는 비동기 메모리의 ATD 블록에 적용하여 전체 레이아웃 면적을 줄일 수 있으며, 속도를 향상시킬 수 있다.Therefore, the present invention can be applied to the ATD block of the asynchronous memory having a repetitive structure because the circuit is simple, and the overall layout area can be reduced, and the speed can be improved.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 따른 개선된 번지 이행 검출기 회로도.3 is an improved bungee transition detector circuit diagram in accordance with the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950065855A KR970055510A (en) | 1995-12-29 | 1995-12-29 | Improved bungee transition detector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950065855A KR970055510A (en) | 1995-12-29 | 1995-12-29 | Improved bungee transition detector |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970055510A true KR970055510A (en) | 1997-07-31 |
Family
ID=66624215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950065855A KR970055510A (en) | 1995-12-29 | 1995-12-29 | Improved bungee transition detector |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970055510A (en) |
-
1995
- 1995-12-29 KR KR1019950065855A patent/KR970055510A/en not_active Application Discontinuation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR970055510A (en) | Improved bungee transition detector | |
KR950027830A (en) | DRAM refresh circuit | |
KR20010045945A (en) | Address transition detection circuit of semiconductor memory | |
KR960039627A (en) | Input buffer of synchronous memory device | |
KR960027286A (en) | Pulse signal generator for operating column decoder | |
KR930008084Y1 (en) | Address transition detecting circuit | |
KR970016965A (en) | Page Mode Output Circuit of Mask ROM | |
KR970055529A (en) | Data input buffer circuit of memory | |
KR960038972A (en) | Output circuit of sense amplifier | |
KR910020726A (en) | Address Transition Detector | |
KR980005003A (en) | The address conversion detection device of the semiconductor memory device | |
KR900003888A (en) | Equilacion pulse generator circuit of Stramatic RAM | |
KR970012702A (en) | Asynchronous Semiconductor Memory Device Using Synchronous Semiconductor Memory Device | |
KR980004979A (en) | Semiconductor memory device | |
KR890012450A (en) | Logic circuit | |
KR930014617A (en) | Output Detection Control Circuit of Sense Amplifier | |
KR950025785A (en) | Semiconductor Memory Device with Address Transition Detection Circuit | |
KR970051112A (en) | Sink RAM with Dual Output Ports | |
KR970023426A (en) | Address buffer and decoder circuit in semiconductor memory | |
KR970055479A (en) | Data Output Buffer Circuit of Semiconductor Memory Device | |
KR970003222A (en) | Self-Timed Logic Combination Circuit | |
KR940017195A (en) | Binary increment circuit | |
KR970055467A (en) | Output buffer of semiconductor memory | |
KR970012741A (en) | Row Address Buffers in Semiconductor Memory Devices | |
KR970076207A (en) | Input stage circuit of Micro-Procesor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |