KR970076207A

KR970076207A - Input stage circuit of Micro-Procesor

Info

Publication number: KR970076207A
Application number: KR1019960018224A
Authority: KR
Inventors: 김인혁
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-05-28
Filing date: 1996-05-28
Publication date: 1997-12-12

Abstract

본 발명은 마이크로프로세서의 입력단 회로에 관해 게시한다. 본 발명은 정보가 입출력되는 하나의 패드와 상기 패드로 입력된 정보가 입력되는 입력 버퍼를 갖는 마이크로프로세서의 입력단 회로에 있어서, 상기 패드를 통해서 서로 다른 여러 가지 정보가 입력될 때 상기 정보를 선별하기 위한 제어 신호를 발생하는 멀티플렉서와, 상기 멀티플렉서의 제어 신호에 의하여 선별된 정보를 입력 버퍼로 전달하는 디코더 및 상기 입력 버퍼에 입력된 정보의 입출력 여부를 결정하는 콘트롤 레지스터(Register)를 구비함으로써 하나의 입출력 패드에 여러 가지 다른 정보를 입력시켜서 사용할 수가 있다. 따라서 마이크로프로세서의 제조 원가도 절감된다.The present invention relates to the input stage circuit of a microprocessor. The present invention provides an input terminal circuit of a microprocessor having a pad for inputting / outputting information and an input buffer for inputting information inputted to the pad, wherein the information is selected when different pieces of information are input through the pad. A multiplexer for generating a control signal, a decoder for transferring information selected by the multiplexer's control signal to an input buffer, and a control register for determining whether to input or output the information input to the input buffer. Various other information can be input to the input / output pad and used. This reduces the manufacturing cost of the microprocessor.

Description

Input stage circuit of Micro-Procesor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 마이크로프로세서의 입력단들 중 하나의 입력단 회로도.2 is an input circuit diagram of one of the input terminals of the microprocessor of the present invention.

Claims

An input terminal circuit of a microprocessor having a pad for inputting / outputting information and an input buffer for inputting information input to the pad, the control signal for selecting the information when different information is input through the pad. Generating a multiplexer; A decoder for transferring the information selected by the control signal of the decoder to an input buffer; And a control register for determining whether to input / output information input to the input buffer.

2. The decoder of claim 1, wherein the decoder comprises: a first inverter and a second inverter having an input terminal connected to an output terminal of the multiplexer, a first input terminal connected to an output terminal of the first inverter, an output terminal of the second inverter, and the pad, respectively. A second end gate connected to an AND gate, an output terminal of the pad and the second inverter, and an input terminal of the first inverter, and an input terminal of the pad and the first inverter to the output terminal of the first inverter and the input terminal of the second inverter, respectively. And a fourth end gate connected to a third end gate and an input terminal of the pad and the first inverter and an input terminal of the second inverter.

※ Note: The disclosure is based on the initial application.