KR970024569A

KR970024569A - Time delay circuit

Info

Publication number: KR970024569A
Application number: KR1019950037288A
Authority: KR
Inventors: 송석범
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-10-26
Filing date: 1995-10-26
Publication date: 1997-05-30

Abstract

본 발명은 디지탈 장치에서 사용되는 시간지연회로에 관한 것으로서, 그 구성은 지연대상신호를 입력하는 제1시간지연소자(10)와; 상기 지연대상 신호를 소정시간지연하여 출력하는 제2시간지연소자(30)및; 상기 제1및 제2시간지연소자(10,30)사이에 접속되어 있고 그리고 제어신호(CS)에 의해서 두가지의 시간지연모드중 하나를 결정하여 그 결정된 모드에 따라 상기 지연대상신호를 시간지연하여 출력하는 시간지연모드결정부(20)를 포함한다. 상술한 본 발명의 시간지연회로에 의하면, 제어신호에 의해 상기 PMOS 트랜지스터가 턴온 또는 턴오프됨에 따라, 상기 제1,2지연소자에 의해서 결정되는 시간동안 입력신호를 시간지연하여 출력하거나, 또는 상기 제1,2지연소자의 게이트거패시턴스와 상기 저항에 의해서 결정되는 시정수시간동안 입력신호를 시간지연하여 출력할 수 있다. 또한, 본 발명의 시간지연회로는 구현된 시간지연소자의 수가 비교적 매우 적기 때문에, 레이아웃의 면적을 감소시킬 수 있을 뿐만아니라, 동작시의 전류소모도 감소시킬 수 있다.The present invention relates to a time delay circuit used in a digital apparatus, the configuration of which comprises a first time delay element (10) for inputting a delay target signal; A second time delay element (30) for delaying and outputting the delay target signal by a predetermined time; Connected between the first and second time delay elements 10 and 30, and one of the two time delay modes is determined by a control signal CS to time delay the delay target signal according to the determined mode. And a time delay mode determination unit 20 for outputting. According to the time delay circuit of the present invention described above, as the PMOS transistor is turned on or off by a control signal, the input signal is delayed and outputted for a time determined by the first and second delay elements, or The input signal may be delayed and output for a time constant time determined by the gate capacitance of the first and second delay elements and the resistance. In addition, the time delay circuit of the present invention can reduce the area of the layout as well as reduce the current consumption during operation because the number of time delay elements implemented is relatively small.

Description

Time delay circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명의 실시예에 따른 시간지연회로의 블럭도;5 is a block diagram of a time delay circuit according to an embodiment of the present invention;

제6도는 제5도에 도시된 시간지연회로의 상세한 회로도;6 is a detailed circuit diagram of the time delay circuit shown in FIG.

제8도는 본 발명의 시간지연회로가 래치회로에 적용한 예를 보여주는 회로도.8 is a circuit diagram showing an example in which the time delay circuit of the present invention is applied to a latch circuit.

Claims

A time delay circuit for use in a digital device, comprising: a first time delay element (10) for inputting a delay target signal; A second time delay element (30) for delaying and outputting the delay target signal by a predetermined time; Connected between the first and second time delay elements 10 and 30, and one of the two time delay modes is determined by a control signal CS to time delay the delay target signal according to the determined mode. A time delay circuit comprising a time delay mode determination unit 20 for outputting.

2. The time delay circuit according to claim 1, wherein the first and second time delay circuits each comprise an inverter.

The switching element 21 according to claim 1, wherein the time delay mode determining unit 20 is connected between the first and second time delay elements 10 and 30 and is switched by the control signal CS. And a resistor (22) connected in parallel with said switching element.

4. The time delay circuit according to claim 3, wherein said switching element (21) is composed of a PMOS transistor to which said control signal is applied through a gate.

※ Note: The disclosure is based on the initial application.