KR970028963A - Port test circuit of microprocessor - Google Patents

Port test circuit of microprocessor Download PDF

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Publication number
KR970028963A
KR970028963A KR1019950040725A KR19950040725A KR970028963A KR 970028963 A KR970028963 A KR 970028963A KR 1019950040725 A KR1019950040725 A KR 1019950040725A KR 19950040725 A KR19950040725 A KR 19950040725A KR 970028963 A KR970028963 A KR 970028963A
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KR
South Korea
Prior art keywords
microprocessor
signal
port
test circuit
transfer gate
Prior art date
Application number
KR1019950040725A
Other languages
Korean (ko)
Inventor
김인혁
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950040725A priority Critical patent/KR970028963A/en
Publication of KR970028963A publication Critical patent/KR970028963A/en

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

어드레스뿐만 아니라 데이터를 모니터링하는 마이크로 프로세서의 포트를 테스트하는 회로가 개시된다.A circuit is disclosed for testing a port of a microprocessor that monitors data as well as an address.

마이크로 프로세서의 포트를 테스트하는 회로에 있어서, 어드레스 신호와 데이터 신호를 선택적으로 출력하는 멀티플렉싱 수단; 상기 멀티플렉싱 수단에서 출력 신호를 게이팅하는 전달 게이트부; 및 상기 전달 게이트부의 출력 상태에 의해 어드레스 신호 혹은 데이터 신호를 버퍼링하는 버퍼부를 포함함을 특징으로 한다.A circuit for testing a port of a microprocessor, comprising: multiplexing means for selectively outputting an address signal and a data signal; A transfer gate part for gating an output signal from the multiplexing means; And a buffer unit which buffers an address signal or a data signal according to an output state of the transfer gate unit.

본 발명에 따른 포트 테스트 회로는 어드레스 신호와 데이터 신호를 모니터링할 수 있으므로 핀을 효율적으로 사용하게 하는 효과를 갖는다.The port test circuit according to the present invention can monitor the address signal and the data signal, so that the pin can be efficiently used.

Description

마이크로 프로세서의 포트 테스트 회로Port test circuit of microprocessor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 포트 테스트 회로의 구성을 보이는 회로도이다.1 is a circuit diagram showing the configuration of a port test circuit according to the present invention.

Claims (1)

마이크로 프로세서의 포트를 테스트하는 회로에 있어서, 어드레스 신호와 데이터 신호를 선택적으로 출력하는 멀티플렉싱 수단; 상기 멀티플렉싱 수단에서 출력 신호를 게이팅하는 전달 게이트부; 및 상기 전달 게이트부의 출력 상태에 의해 어드레스 신호 혹은 데이터 신호를 버퍼링하는 버퍼부를 포함하는 포트 테스트 회로.A circuit for testing a port of a microprocessor, comprising: multiplexing means for selectively outputting an address signal and a data signal; A transfer gate part for gating an output signal from the multiplexing means; And a buffer unit configured to buffer an address signal or a data signal according to an output state of the transfer gate unit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040725A 1995-11-10 1995-11-10 Port test circuit of microprocessor KR970028963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950040725A KR970028963A (en) 1995-11-10 1995-11-10 Port test circuit of microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950040725A KR970028963A (en) 1995-11-10 1995-11-10 Port test circuit of microprocessor

Publications (1)

Publication Number Publication Date
KR970028963A true KR970028963A (en) 1997-06-26

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ID=66587052

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950040725A KR970028963A (en) 1995-11-10 1995-11-10 Port test circuit of microprocessor

Country Status (1)

Country Link
KR (1) KR970028963A (en)

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