KR940017197A - Input Buffer - Google Patents

Input Buffer Download PDF

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Publication number
KR940017197A
KR940017197A KR1019920026879A KR920026879A KR940017197A KR 940017197 A KR940017197 A KR 940017197A KR 1019920026879 A KR1019920026879 A KR 1019920026879A KR 920026879 A KR920026879 A KR 920026879A KR 940017197 A KR940017197 A KR 940017197A
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KR
South Korea
Prior art keywords
input
node
pad
transistor
signal
Prior art date
Application number
KR1019920026879A
Other languages
Korean (ko)
Other versions
KR950000356B1 (en
Inventor
김정필
Original Assignee
김주용
현대전자산업 주식회사
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920026879A priority Critical patent/KR950000356B1/en
Publication of KR940017197A publication Critical patent/KR940017197A/en
Application granted granted Critical
Publication of KR950000356B1 publication Critical patent/KR950000356B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 본딩 옵션 패드의 출력이 게이트에 입력되고 한쪽 노드가 노드③에 연결된 트랜지스터 N45와, 상기 트랜지스터 N45의 한쪽 노드와 접지사이에 채널이 형성되고 게이트에 입력 패드의 신호(101)가 입력되는 트랜지스터 N46과, 상기 본딩 옵션 패드 출력의 반전된 신호가 게이트에 입력되고 한쪽 노드가 노드③에 연결된 트랜지스터 N47과, 상기 트랜지스터 N47의 한쪽 노드와 접지사이에 채널이 형성되고 게이트에 다른 입력 패드의 신호(102)가 입력되는 트랜지스터 N48로 구성되어 본딩 옵션 패드의 출력 상태에 따라 두 입력 패드중 한개의 패드값만이 노드③을 통하여 입력 버퍼에 전달되는 것을 특징으로 한다.In the present invention, the output of the bonding option pad is input to the gate and one node is connected to node ③, and a channel is formed between one node of the transistor N45 and ground and the signal of the input pad is input to the gate. A transistor is formed between the transistor N46, the transistor N47 having the inverted signal of the bonding option pad output input to the gate, and one node connected to the node ③, and a channel is formed between one node of the transistor N47 and ground, and the signal of the other input pad is formed on the gate. 102 is configured to input transistor N48, and according to the output state of the bonding option pad, only one pad value of the two input pads is transferred to the input buffer through the node ③.

Description

입력 버퍼(Buffer)Input Buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 3 도는 본 발명에 따른 X-어드레스 버퍼, 제 4 도는 본 발명에 따른 데이터 입력 버퍼.3 is an X-address buffer according to the present invention, and FIG. 4 is a data input buffer according to the present invention.

Claims (3)

한개의 입력 버퍼를 사용하게 2개의 입력 패드에 대하여 공통으로 사용하는 경우에 있어서, 본딩 옵션 패드의 출력이 게이트에 입력되고 한쪽 노드가 노드③에 연결된 트랜지스터 N45와, 상기 트랜지스터 N45의 한쪽 노드와 접지사이에 채널이형성되고 게이트에 입력 패드의 신호(IO1)가 입력되는 트랜지스터 N46과, 상기 본딩 옵션 패드 출력의 반전된 신호가 게이트에 입력되고 한쪽 노드가 노드③에 연결된 트랜지스터 N47과, 상기 트랜지스터 N47의 한쪽 노드와 접지사이에 채널이형성되고 게이트에 다른 입력 패드의 신호(IO2)가 입력되는 트랜지스터 N48로 구성되어 본딩 옵션 패드의 출력 상태에 따라 두 입력 패스중 한개의 패드값만이 노드③을 통하여 입력 버퍼에 전달되는 것을 특징으로 하는 입력 버퍼 회로.In the case where one input buffer is used in common for two input pads, a transistor N45 having an output of a bonding option pad input to a gate and one node connected to a node ③, and one node of the transistor N45 and ground A transistor N46 in which a channel is formed and a signal IO1 of an input pad is input to a gate, a transistor N47 in which an inverted signal of the bonding option pad output is input to a gate and one node is connected to a node ③, and the transistor N47 A channel is formed between one node and ground, and the transistor N48 is configured to input the signal IO2 of the other input pad to the gate. Only one pad value of the two input paths is connected to node ③ according to the output state of the bonding option pad. The input buffer circuit, characterized in that the transfer to the input buffer through. 제 1항에 있어서, 상기 입력 패드 신호 대신에 한개의 입력 패드 신호(어드레스 패드)와 한개의 내부 신호(CBR 카운터 출력)가 입력되어 상기 두 신호중 하나만이 입력 버퍼에 전달되는 것을 특징으로 하는 입력 버퍼 회로.The input buffer of claim 1, wherein one input pad signal (address pad) and one internal signal (CBR counter output) are input instead of the input pad signal, and only one of the two signals is transmitted to the input buffer. Circuit. 제 1 항에 있어서, 한개의 입력 버퍼를 상기 노드③과 접지에 병렬로 연결된 두개 이상의 입력 패드에 대하여 공통으로사용하는 것을 특징으로 하는 입력 버퍼 회로.The input buffer circuit according to claim 1, wherein one input buffer is commonly used for two or more input pads connected in parallel to the node ③ and ground. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920026879A 1992-12-30 1992-12-30 Input buffer KR950000356B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920026879A KR950000356B1 (en) 1992-12-30 1992-12-30 Input buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920026879A KR950000356B1 (en) 1992-12-30 1992-12-30 Input buffer

Publications (2)

Publication Number Publication Date
KR940017197A true KR940017197A (en) 1994-07-26
KR950000356B1 KR950000356B1 (en) 1995-01-13

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ID=19348032

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920026879A KR950000356B1 (en) 1992-12-30 1992-12-30 Input buffer

Country Status (1)

Country Link
KR (1) KR950000356B1 (en)

Also Published As

Publication number Publication date
KR950000356B1 (en) 1995-01-13

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