KR930003549A - Input buffer of memory - Google Patents

Input buffer of memory Download PDF

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Publication number
KR930003549A
KR930003549A KR1019910011888A KR910011888A KR930003549A KR 930003549 A KR930003549 A KR 930003549A KR 1019910011888 A KR1019910011888 A KR 1019910011888A KR 910011888 A KR910011888 A KR 910011888A KR 930003549 A KR930003549 A KR 930003549A
Authority
KR
South Korea
Prior art keywords
input
input buffer
channel mosfet
memory
drain
Prior art date
Application number
KR1019910011888A
Other languages
Korean (ko)
Inventor
장성준
이상호
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910011888A priority Critical patent/KR930003549A/en
Publication of KR930003549A publication Critical patent/KR930003549A/en

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Abstract

내용 없음.No content.

Description

메모리의 입력버퍼Input buffer of memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 입력버퍼의 회로도,3 is a circuit diagram of an input buffer according to the present invention,

제4도는 제3도의 각 부분의 신호파형도.4 is a signal waveform diagram of each part of FIG.

Claims (2)

메모리의 입력버퍼에 있어서; 전원(Vdd)에 소오스가 연결되고 게이트는 접지된 제1p채널 MOSFET(MP4),상기 제1P채널 MOSFET(MP3)의 드레인에 드레인을 연결하고 버퍼동작신호(BES)를 소오스 입력으로 하며 상기 어드레스를 게이트 입력으로 하는 n채널 MOSFET(MN3)로 구성되는 것을 특징으로 하는 입력버퍼.An input buffer of a memory; A source is connected to the power supply Vdd and a gate is connected to the drain of the first P-channel MOSFET MP4 and the drain of the first P-channel MOSFET MP3, and the buffer operation signal BES is a source input. An input buffer comprising an n-channel MOSFET (MN3) serving as a gate input. 제1항에 있어서, 상기 n채널 MOSFET(MN3)는 상기 제2p채널 MOSFET의 드레인에 소오스를 연결하고 버포동작신호(BES)를 드레인의 입력으로 하여 구성되는 것을 특징으로 하는 입력 버퍼.The input buffer according to claim 1, wherein the n-channel MOSFET (MN3) is configured by connecting a source to a drain of the second p-channel MOSFET and using a buffer operation signal (BES) as an input of a drain. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910011888A 1991-07-12 1991-07-12 Input buffer of memory KR930003549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910011888A KR930003549A (en) 1991-07-12 1991-07-12 Input buffer of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910011888A KR930003549A (en) 1991-07-12 1991-07-12 Input buffer of memory

Publications (1)

Publication Number Publication Date
KR930003549A true KR930003549A (en) 1993-02-24

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ID=67440615

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910011888A KR930003549A (en) 1991-07-12 1991-07-12 Input buffer of memory

Country Status (1)

Country Link
KR (1) KR930003549A (en)

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